MCQOPTIONS
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MCQOPTIONS
This section includes 657 Mcqs, each offering curated multiple-choice questions to sharpen your Testing Subject knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
The data stored in a Mask ROM (MROM) is ___________. |
| A. | permanent |
| B. | volatile |
| C. | erasable |
| D. | temporary |
| Answer» B. volatile | |
| 2. |
An SRAM storage cell is less complex than a DRAM storage cell. |
| A. | True |
| B. | False |
| Answer» C. | |
| 3. |
The key advantage of the EPROM is its ability to erase only a single byte of stored data. |
| A. | True |
| B. | False |
| Answer» C. | |
| 4. |
Memory configuration refers to the organization of storage bits within a memory. |
| A. | True |
| B. | False |
| Answer» B. False | |
| 5. |
ROM stands for read-only memory. |
| A. | True |
| B. | False |
| Answer» B. False | |
| 6. |
To avoid data loss, SRAM must be refreshed every few milliseconds. |
| A. | True |
| B. | False |
| Answer» C. | |
| 7. |
Which component is considered to be an "OFF" device? |
| A. | transistor |
| B. | JFET |
| C. | D-MOSFET |
| D. | E-MOSFET |
| Answer» E. | |
| 8. |
The common-source JFET amplifier has: |
| A. | a very high input impedance and a relatively low voltage gain |
| B. | a high input impedance and a very high voltage gain |
| C. | a high input impedance and a voltage gain less than 1 |
| D. | no voltage gain |
| Answer» B. a high input impedance and a very high voltage gain | |
| 9. |
Using voltage-divider biasing, what is the voltage at the gate VGS? |
| A. | 5.2 V |
| B. | 4.2 V |
| C. | 3.2 V |
| D. | 2.2 V |
| Answer» B. 4.2 V | |
| 10. |
In general, _________ are used when a small amount of read/write is required. |
| A. | EEPROMs |
| B. | PROMs |
| C. | SRAMs |
| D. | DRAMs |
| Answer» D. DRAMs | |
| 11. |
The process of entering data into the ROM is called ___________. |
| A. | burning in |
| B. | configuration |
| C. | internal decoding |
| D. | addressing |
| Answer» B. configuration | |
| 12. |
To reduce the number of pins on the IC package, manufacturers often use ___________. |
| A. | MOSFET architecture |
| B. | address multiplexing |
| C. | address decoding |
| D. | address demultiplexing |
| Answer» C. address decoding | |
| 13. |
The periodic recharging of DRAM memory cells is called ___________. |
| A. | multiplexing |
| B. | bootstrapping |
| C. | refreshing |
| D. | flashing |
| Answer» D. flashing | |
| 14. |
________ is an example of read/write memory. |
| A. | PROM |
| B. | EEPROM |
| C. | RAM |
| D. | MROM |
| Answer» D. MROM | |
| 15. |
The overall input capacitance of a dual-gate D-MOSFET is lower because the devices are usually connected: |
| A. | in parallel |
| B. | with separate insulation |
| C. | with separate inputs |
| D. | in series |
| Answer» E. | |
| 16. |
When the JFET is no longer able to control the current, this point is called the: |
| A. | breakdown region |
| B. | depletion region |
| C. | saturation point |
| D. | pinch-off region |
| Answer» B. depletion region | |
| 17. |
An AND gate and two INVERTERs can be connected to act as a basic decoder. |
| A. | True |
| B. | False |
| Answer» B. False | |
| 18. |
Parity checking can only detect an odd number of errors. |
| A. | True |
| B. | False |
| Answer» B. False | |
| 19. |
A sixteen-input multiplexer will need three data select input control lines. |
| A. | True |
| B. | False |
| Answer» C. | |
| 20. |
A hexadecimal decoder selects one of sixteen outputs depending on the 8-bit binary input applied. |
| A. | True |
| B. | False |
| Answer» C. | |
| 21. |
A multiplexer is a device that chooses which output to send an input to by means of select lines. |
| A. | True |
| B. | False |
| Answer» B. False | |
| 22. |
Which JFET configuration would connect a high-resistance signal source to a low-resistance load? |
| A. | source follower |
| B. | common-source |
| C. | common-drain |
| D. | common-gate |
| Answer» B. common-source | |
| 23. |
How will electrons flow through a p-channel JFET? |
| A. | from source to drain |
| B. | from source to gate |
| C. | from drain to gate |
| D. | from drain to source |
| Answer» E. | |
| 24. |
When VGS = 0 V, a JFET is: |
| A. | saturated |
| B. | an analog device |
| C. | an open switch |
| D. | cut off |
| Answer» B. an analog device | |
| 25. |
When applied input voltage varies the resistance of a channel, the result is called: |
| A. | saturization |
| B. | polarization |
| C. | cutoff |
| D. | field effect |
| Answer» E. | |
| 26. |
When is a vertical channel E-MOSFET used? |
| A. | for high frequencies |
| B. | for high voltages |
| C. | for high currents |
| D. | for high resistances |
| Answer» D. for high resistances | |
| 27. |
JFET terminal "legs" are connections to the drain, the gate, and the: |
| A. | channel |
| B. | source |
| C. | substrate |
| D. | cathode |
| Answer» C. substrate | |
| 28. |
When testing an n-channel D-MOSFET, resistance G to D = , resistance G to S = , resistance D to SS = and 500 , depending on the polarity of the ohmmeter, and resistance D to S = 500 . What is wrong? |
| A. | short D to S |
| B. | open G to D |
| C. | open D to SS |
| D. | nothing |
| Answer» E. | |
| 29. |
A MOSFET has how many terminals? |
| A. | 2 or 3 |
| B. | 3 |
| C. | 4 |
| D. | 3 or 4 |
| Answer» E. | |
| 30. |
What is the input impedance of a common-gate configured JFET? |
| A. | very low |
| B. | low |
| C. | high |
| D. | very high |
| Answer» B. low | |
| 31. |
A very simple bias for a D-MOSFET is called: |
| A. | self biasing |
| B. | gate biasing |
| C. | zero biasing |
| D. | voltage-divider biasing |
| Answer» D. voltage-divider biasing | |
| 32. |
With the E-MOSFET, when gate input voltage is zero, drain current is: |
| A. | at saturation |
| B. | zero |
| C. | I |
| D. | <sub>DSS</sub> |
| E. | widening the channel |
| Answer» C. I | |
| 33. |
With a 30-volt VDD, and an 8-kilohm drain resistor, what is the E-MOSFET Q point voltage, with ID = 3 mA? |
| A. | 6 V |
| B. | 10 V |
| C. | 24 V |
| D. | 30 V |
| Answer» B. 10 V | |
| 34. |
When an input signal reduces the channel size, the process is called: |
| A. | enhancement |
| B. | substrate connecting |
| C. | gate charge |
| D. | depletion |
| Answer» E. | |
| 35. |
With a JFET, a ratio of output current change against an input voltage change is called: |
| A. | transconductance |
| B. | siemens |
| C. | resistivity |
| D. | gain |
| Answer» B. siemens | |
| 36. |
Which type of JFET bias requires a negative supply voltage? |
| A. | feedback |
| B. | source |
| C. | gate |
| D. | voltage divider |
| Answer» D. voltage divider | |
| 37. |
How will a D-MOSFET input impedance change with signal frequency? |
| A. | As frequency increases input impedance increases. |
| B. | As frequency increases input impedance is constant. |
| C. | As frequency decreases input impedance increases. |
| D. | As frequency decreases input impedance is constant. |
| Answer» D. As frequency decreases input impedance is constant. | |
| 38. |
The type of bias most often used with E-MOSFET circuits is: |
| A. | constant current |
| B. | drain-feedback |
| C. | voltage-divider |
| D. | zero biasing |
| Answer» C. voltage-divider | |
| 39. |
A technique of addressing storage cells on a dynamic RAM that sequentially uses the same inputs for the row and column addresses of the cell is called________. |
| A. | flash conversion |
| B. | dynamic refresh |
| C. | address multiplexing |
| D. | address strobe |
| Answer» D. address strobe | |
| 40. |
The time interval between the memory receiving a new address input and the data being available is called _________. |
| A. | access time |
| B. | bus speed |
| C. | read/write speed |
| D. | write/data speed |
| Answer» B. bus speed | |
| 41. |
Advantage(s) of an EEPROM over an EPROM is (are): |
| A. | the EPROM can be erased with ultraviolet light in much less time than an EEPROM |
| B. | the EEPROM can be erased and reprogrammed without removal from the circuit |
| C. | the EEPROM has the ability to erase and reprogram individual words |
| D. | the EEPROM can erase and reprogram individual words without removal from the circuit |
| Answer» E. | |
| 42. |
Memory that loses its contents when power is lost is: |
| A. | nonvolatile |
| B. | volatile |
| C. | random |
| D. | static |
| Answer» C. random | |
| 43. |
Select the best description of the fusible-link PROM. |
| A. | user programmable, one-time programmable |
| B. | manufacturer programmable, one-time programmable |
| C. | user programmable, reprogrammable |
| D. | manufacturer programmable, reprogrammable |
| Answer» B. manufacturer programmable, one-time programmable | |
| 44. |
An encoder circuit is designed to generate specific codes. |
| A. | True |
| B. | False |
| Answer» C. | |
| 45. |
A decoder with two inputs will have two outputs for the decoded value. |
| A. | True |
| B. | False |
| Answer» C. | |
| 46. |
A magnitude comparator outputs the highest or lowest value of its inputs depending on control signals. |
| A. | True |
| B. | False |
| Answer» C. | |
| 47. |
Which type of decoder will select one of sixteen outputs, depending on the 4-bit binary input value? |
| A. | hexadecimal |
| B. | dual octal outputs |
| C. | binary-to-hexadecimal |
| D. | hexadecimal-to-binary |
| Answer» B. dual octal outputs | |
| 48. |
Which digital system translates coded characters into a more intelligible form? |
| A. | encoder |
| B. | display |
| C. | counter |
| D. | decoder |
| Answer» E. | |
| 49. |
The basic programmable logic array (PLA) contains a set of _____ gates, _____ gates, and ______ gates. |
| A. | NOT, NAND, OR |
| B. | NOT, AND, OR |
| C. | NAND, AND, NOR |
| D. | OR, NOR, AND |
| Answer» C. NAND, AND, NOR | |
| 50. |
When an input delta of 2 V produces a transconductance of 1.5 mS, what is the drain current delta? |
| A. | 666 mA |
| B. | 3 mA |
| C. | 0.75 mA |
| D. | 0.5 mA |
| Answer» C. 0.75 mA | |