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This section includes 6 Mcqs, each offering curated multiple-choice questions to sharpen your GATE practice papers - Electronics & Communication knowledge and support exam preparation. Choose a topic below to get started.
1. |
Which process plays a crucial role in transforming the pattern or layout on the working mask of silicon wafer in an IC fabrication mechanism? (Marks : 01) |
A. | Wafer Cleaning |
B. | Mask Making |
C. | Epitaxy |
D. | Photo-lithography |
Answer» E. | |
2. |
The ratio of collector current to emitter current by maintaining collector to base voltage at a constant levelis usuallytermed as ___________ (Marks : 01) |
A. | Common Emitter Amplification Factor |
B. | Common Collector Amplification Factor |
C. | Common Base Amplification Factor |
D. | None of the above |
Answer» D. None of the above | |
3. |
Which phenomenon in BJT is responsible for reduction in the effective base-width due to reverse-biasing of base-collector junction? (Marks : 01) |
A. | Hall Effect |
B. | Early Effect |
C. | Fermi-Level Effect |
D. | All of the above |
Answer» C. Fermi-Level Effect | |
4. |
Consider the below mentioned assertions :A1 : Increase in doping level of p-type moves E towards the centre A2 : Increase in doping level of p-type moves E away from the centreA3: Increase in doping level of p-type results in downward shifting in EA4 : Increase in doping level of p-type results in an upward shifting in EWhich among them is/are correct in accordance to the existence of fermi-level effect in P-type semiconductor?(Marks : 02) |
A. | A1 & A3 |
B. | A2 & A4 |
C. | A1 & A4 |
D. | A2 & A3 |
Answer» B. A2 & A4 | |
5. |
Consider the below mentioned statements.A1. Reduction in channel width & cross-sectional areaA2. Reduction in current density of channelWhich among them are the possible consequences in JFET upon the application of drain-to-source voltage (V)? (Marks : 02) |
A. | Only A1 is true |
B. | Both A1 & A2 are true but A2 is not a reason for A1 |
C. | Both A1 & A2 are true but A2 is a reason for A1 |
D. | Both A1 & A2 are false |
Answer» B. Both A1 & A2 are true but A2 is not a reason for A1 | |
6. |
Consider the assertions S1,S2,S3 & S4 S1 : SiOacts as an isolation layer between the junctions in IC fabrication processS2 : SiOacts as an isolation equipment/ materialbetween thedifferent devicesS3: SiOacts as a passivation layer by preventing undesired impurities over the silicon surface.S4 : SiOactsas a di-electric between poly-silicon gate and the channel of semiconductorWhich among them is/ are precise functions of silicon dioxide in an ion implantationprocess?(Marks : 01) |
A. | S1: Correct, S2: Correct, S3:Correct , S4: Correct |
B. | S1: Correct, S2: Incorrect, S3: Correct , S4 : Correct |
C. | S1: Correct, S2: Correct, S3 :Incorrect , S4 : Correct |
D. | S1: Correct, S2: Correct, S3 : Correct, S4 : Incorrect |
Answer» B. S1: Correct, S2: Incorrect, S3: Correct , S4 : Correct | |