MCQOPTIONS
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MCQOPTIONS
This section includes 242 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
For the device shown here, assume the D input is LOW, both S inputs are LOW and the input is LOW. What is the status of the Y’ outputs? |
| A. | d |
| B. | a |
| C. | c |
| D. | b |
| Answer» B. a | |
| 2. |
There are many situations in logic design in which simplification of logic expression is possible in terms of XOR and operations. |
| A. | x-nor |
| B. | xor |
| C. | nor |
| D. | nand |
| Answer» B. xor | |
| 3. |
The number of literals in the expression F=X.Y’ + Z are |
| A. | 4 |
| B. | 3 |
| C. | 2 |
| D. | 1 |
| Answer» C. 2 | |
| 4. |
There are cells in a 4-variable K-map. |
| A. | 12 |
| B. | 16 |
| C. | 18 |
| D. | 8 |
| Answer» C. 18 | |
| 5. |
A sequential logic can’t be executed by concurrent statements only. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 6. |
A digital system consists of types of circuits. |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» B. 3 | |
| 7. |
If the decimal number is a fraction then its binary equivalent is obtained by the number continuously by 2. |
| A. | dividing |
| B. | multiplying |
| C. | adding |
| D. | subtracting |
| Answer» C. adding | |
| 8. |
The following timing diagram shows flip flop. |
| A. | t flip-flop |
| B. | d flip-flop |
| C. | sr flip-flop |
| D. | jk flip-flop |
| Answer» C. sr flip-flop | |
| 9. |
Don’t care conditions can be used for simplifying Boolean expressions in |
| A. | registers |
| B. | terms |
| C. | k-maps |
| D. | latches |
| Answer» D. latches | |
| 10. |
Which of the following sequential circuit doesn’t need a clock signal? |
| A. | flip flop |
| B. | asynchronous counter |
| C. | shift register |
| D. | latch |
| Answer» E. | |
| 11. |
The complement term for X’.Y’.Z + X.Y will be |
| A. | xyz’+x’y’ |
| B. | (x+y+z’)(x’+y’) |
| C. | (x+y+z’)(x’+y) |
| D. | (x+y+z’)(x’+y) |
| Answer» C. (x+y+z’)(x’+y) | |
| 12. |
The K-map based Boolean reduction is based on the following Unifying Theorem: A + A’ = 1. |
| A. | impact |
| B. | non impact |
| C. | force |
| D. | complementarity |
| Answer» C. force | |
| 13. |
The use of VHDL can be done in ways. |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» C. 4 | |
| 14. |
A three digit decimal number requires for representation in the conventional BCD format. |
| A. | 3 bits |
| B. | 6 bits |
| C. | 12 bits |
| D. | 24 bits |
| Answer» D. 24 bits | |
| 15. |
A user doesn’t want to use the IF statement for detecting clock edge. It is possible to do the same by using any other keyword in VHDL. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 16. |
Entries known as mapping. |
| A. | diagonal |
| B. | straight |
| C. | k |
| D. | boolean |
| Answer» B. straight | |
| 17. |
If the two numbers are unsigned, the bit conditions of interest are the carry and a possible result. |
| A. | input, zero |
| B. | output, one |
| C. | input, one |
| D. | output, zero |
| Answer» E. | |
| 18. |
The process used for implementation of sequential logic in VHDL is called process. |
| A. | sequential process |
| B. | combinational process |
| C. | clocked process |
| D. | unclocked process |
| Answer» D. unclocked process | |
| 19. |
expressions can be implemented using either (1) 2-level AND-OR logic circuits or (2) 2-level NAND logic circuits. |
| A. | pos |
| B. | literals |
| C. | sop |
| D. | pos |
| Answer» D. pos | |
| 20. |
Express the decimal format of the signed binary number (101010)2 . |
| A. | 10 |
| B. | 12 |
| C. | -12 |
| D. | -10 |
| Answer» E. | |
| 21. |
For programmable logic functions, which type of PLD should be used? |
| A. | pla |
| B. | pal |
| C. | cpld |
| D. | sld |
| Answer» C. cpld | |
| 22. |
Applications of PLAs are |
| A. | registered pals |
| B. | configurable pals |
| C. | pal programming |
| D. | all of the mentioned |
| Answer» E. | |
| 23. |
The full form of VLSI is |
| A. | very long single integration |
| B. | very least scale integration |
| C. | very large scale integration |
| D. | very long scale integration |
| Answer» D. very long scale integration | |
| 24. |
In FPGA, vertical and horizontal directions are separated by |
| A. | a line |
| B. | a channel |
| C. | a strobe |
| D. | a flip-flop |
| Answer» C. a strobe | |
| 25. |
The FPGA refers to |
| A. | first programmable gate array |
| B. | field programmable gate array |
| C. | first program gate array |
| D. | field program gate array |
| Answer» C. first program gate array | |
| 26. |
If a PAL has been programmed once |
| A. | its logic capacity is lost |
| B. | its outputs are only active high |
| C. | its outputs are only active low |
| D. | it cannot be reprogrammed |
| Answer» E. | |
| 27. |
The difference between a PAL & a PLA is |
| A. | pals and plas are the same thing |
| B. | the pla has a programmable or plane and a programmable and plane, while the pal only has a programmable and plane |
| C. | the pal has a programmable or plane and a programmable and plane, while the pla only has a programmable and plane |
| D. | the pal has more possible product terms than the pla |
| Answer» C. the pal has a programmable or plane and a programmable and plane, while the pla only has a programmable and plane | |
| 28. |
Which type of device FPGA are? |
| A. | sld |
| B. | srom |
| C. | eprom |
| D. | pld |
| Answer» E. | |
| 29. |
The complex programmable logic device contains several PLD blocks and |
| A. | a language compiler |
| B. | and/or arrays |
| C. | global interconnection matrix |
| D. | field-programmable switches |
| Answer» D. field-programmable switches | |
| 30. |
A PLA is similar to a ROM in concept except that |
| A. | it hasn’t capability to read only |
| B. | it hasn’t capability to read or write operation |
| C. | it doesn’t provide full decoding to the variables |
| D. | it hasn’t capability to write only |
| Answer» D. it hasn’t capability to write only | |
| 31. |
PLA is used to implement |
| A. | a complex sequential circuit |
| B. | a simple sequential circuit |
| C. | a complex combinational circuit |
| D. | a simple combinational circuit |
| Answer» D. a simple combinational circuit | |
| 32. |
6 PROGRAMMABLE ARRAY LOGIC |
| A. | pla |
| B. | pal |
| C. | cpld |
| D. | sld |
| Answer» C. cpld | |
| 33. |
PLA contains |
| A. | and and or arrays |
| B. | nand and or arrays |
| C. | not and and arrays |
| D. | nor and or arrays |
| Answer» B. nand and or arrays | |
| 34. |
Outputs of the AND gate in PLD is known as |
| A. | input lines |
| B. | output lines |
| C. | strobe lines |
| D. | control lines |
| Answer» C. strobe lines | |
| 35. |
The inputs in the PLD is given through |
| A. | nand gates |
| B. | or gates |
| C. | nor gates |
| D. | and gates |
| Answer» E. | |
| 36. |
PAL refers to |
| A. | programmable array loaded |
| B. | programmable logic array |
| C. | programmable array logic |
| D. | programmable and logic |
| Answer» D. programmable and logic | |
| 37. |
How many types of PLD is? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» B. 3 | |
| 38. |
How many 16K * 4 RAMs are required to achieve a memory with a capacity of 64K and a word length of 8 bits? |
| A. | 2 |
| B. | 4 |
| C. | 6 |
| D. | 8 |
| Answer» E. | |
| 39. |
Why antifuses are implemented in a PLD? |
| A. | to protect from high voltage |
| B. | to increase the memory |
| C. | to implement the programmes |
| D. | as a switching devices |
| Answer» D. as a switching devices | |
| 40. |
PLA refers to |
| A. | programmable loaded array |
| B. | programmable array logic |
| C. | programmable logic array |
| D. | programmed array logic |
| Answer» D. programmed array logic | |
| 41. |
How many 1024 * 1 RAM chips are required to construct a 1024 * 8 memory system? |
| A. | 4 |
| B. | 6 |
| C. | 8 |
| D. | 12 |
| Answer» D. 12 | |
| 42. |
PLD contains a large number of |
| A. | flip-flops |
| B. | gates |
| C. | registers |
| D. | all of the mentioned |
| Answer» E. | |
| 43. |
IC 4116 is organised as |
| A. | 512 * 4 |
| B. | 16 * 1 |
| C. | 32 * 4 |
| D. | 64 * 2 |
| Answer» D. 64 * 2 | |
| 44. |
How memory expansion is done? |
| A. | by increasing the supply voltage of the memory ics |
| B. | by decreasing the supply voltage of the memory ics |
| C. | by connecting memory ics together |
| D. | by separating memory ics |
| Answer» D. by separating memory ics | |
| 45. |
How many address bits are required to select memory location in Memory decoder? |
| A. | 4 kb |
| B. | 8 kb |
| C. | 12 kb |
| D. | 16 kb |
| Answer» D. 16 kb | |
| 46. |
In ROM, each bit combination that comes out of the output lines is called |
| A. | memory unit |
| B. | storage class |
| C. | data word |
| D. | address |
| Answer» D. address | |
| 47. |
Which is not a removable drive? |
| A. | zip |
| B. | hard disk |
| C. | super disk |
| D. | jaz |
| Answer» D. jaz | |
| 48. |
What is memory decoding? |
| A. | the process of memory ic used in a digital system is overloaded with data |
| B. | the process of memory ic used in a digital system is selected for the range of address assigned |
| C. | the process of memory ic used in a digital system is selected for the range of data assigned |
| D. | the process of memory ic used in a digital system is overloaded with data allocated in memory cell |
| Answer» C. the process of memory ic used in a digital system is selected for the range of data assigned | |
| 49. |
In ROM, each bit is a combination of the address variables is called |
| A. | memory unit |
| B. | storage class |
| C. | data word |
| D. | address |
| Answer» E. | |
| 50. |
ROM has the capability to perform |
| A. | write operation only |
| B. | read operation only |
| C. | both write and read operation |
| D. | erase operation |
| Answer» C. both write and read operation | |