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This section includes 358 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
301. |
In an ECL the output is taken from |
A. | emitter |
B. | base |
C. | collector |
D. | junction of emitter and base |
Answer» D. junction of emitter and base | |
302. |
Which logic is the fastest of all the logic families? |
A. | ttl |
B. | ecl |
C. | htl |
D. | dtl |
Answer» C. htl | |
303. |
Sometimes ECL can also be named as |
A. | eel |
B. | cel |
C. | cml |
D. | ccl |
Answer» D. ccl | |
304. |
The full form of ECL is |
A. | emitter-collector logic |
B. | emitter-complementary logic |
C. | emitter-coupled logic |
D. | emitter-cored logic |
Answer» D. emitter-cored logic | |
305. |
Which chip were the first RTC and CMOS RAM chip to be used in early IBM computers, capable of storing a total of 64 bytes? |
A. | the samsung 146818 |
B. | the samsung 146819 |
C. | the motorola 146818 |
D. | the motorola 146819 |
Answer» D. the motorola 146819 | |
306. |
Semiconductors are made of |
A. | ge and si |
B. | si and pb |
C. | ge and pb |
D. | pb and au |
Answer» B. si and pb | |
307. |
CMOS logic dissipates power than NMOS logic circuits. |
A. | more |
B. | less |
C. | equal |
D. | very high |
Answer» C. equal | |
308. |
An important characteristic of a CMOS circuit is the |
A. | noise immunity |
B. | duality |
C. | symmetricity |
D. | noise margin |
Answer» C. symmetricity | |
309. |
CMOS behaves as a/an |
A. | adder |
B. | subtractor |
C. | inverter |
D. | comparator |
Answer» D. comparator | |
310. |
CMOS technology is used in |
A. | inverter |
B. | microprocessor |
C. | digital logic |
D. | both microprocessor and digital logic |
Answer» E. | |
311. |
Two important characteristics of CMOS devices are |
A. | high noise immunity |
B. | low static power consumption |
C. | high resistivity |
D. | both high noise immunity and low static power consumption |
Answer» E. | |
312. |
CMOS is also sometimes referred to as |
A. | capacitive metal oxide semiconductor |
B. | capacitive symmetry metal oxide semiconductor |
C. | complementary symmetry metal oxide semiconductor |
D. | complemented symmetry metal oxide semiconductor |
Answer» D. complemented symmetry metal oxide semiconductor | |
313. |
The full form of COS-MOS is |
A. | complementary symmetry metal oxide semiconductor |
B. | complementary systematic metal oxide semiconductor |
C. | capacitive symmetry metal oxide semiconductor |
D. | complemented systematic metal oxide semiconductor |
Answer» B. complementary systematic metal oxide semiconductor | |
314. |
The full form of CMOS is |
A. | capacitive metal oxide semiconductor |
B. | capacitive metallic oxide semiconductor |
C. | complementary metal oxide semiconductor |
D. | complemented metal oxide semiconductor |
Answer» D. complemented metal oxide semiconductor | |
315. |
The latest entrant to the ECL family is |
A. | ecl 10k |
B. | ecl 100k |
C. | ecl 1000k |
D. | ecl 10000k |
Answer» C. ecl 1000k | |
316. |
Motorola has offered MECL circuits in logic families. |
A. | 3 |
B. | 4 |
C. | 5 |
D. | 6 |
Answer» D. 6 | |
317. |
The full form of MECL is |
A. | mono emitter coupled logic |
B. | motorola emitter coupled logic |
C. | motorola emitter capacitor logic |
D. | both mono emitter and motorola coupled logic |
Answer» C. motorola emitter capacitor logic | |
318. |
The basic idea of basic CML circuit came from an |
A. | inverter |
B. | buffer |
C. | transistor |
D. | both inverter and buffer |
Answer» E. | |
319. |
Schottky families prevent the saturating using |
A. | transistors |
B. | schottky transistors |
C. | diodes |
D. | schottky diodes |
Answer» E. | |
320. |
The first CML logic was introduced by General Electric in |
A. | 1960 |
B. | 1981 |
C. | 1961 |
D. | 1990 |
Answer» D. 1990 | |
321. |
The method of connecting a driving device to a loading device is known as |
A. | compatibility |
B. | interface |
C. | sourcing |
D. | sinking |
Answer» C. sourcing | |
322. |
Compatibility refers to |
A. | the output of a circuit should match with the input of another circuit |
B. | the output of a circuit should match with the input of the same circuit |
C. | the input of a circuit should match with the output of another circuit |
D. | the input of a circuit should match with the output of same circuit |
Answer» B. the output of a circuit should match with the input of the same circuit | |
323. |
A disadvantage of DTL is |
A. | the input transistor to the resister |
B. | the input resister to the transistor |
C. | the increased fan-in |
D. | the increased fan-out |
Answer» C. the increased fan-in | |
324. |
To increase fan-out of the gate in DTL |
A. | an additional capacitor may be used |
B. | an additional resister may be used |
C. | an additional transistor and diode may be used |
D. | only an additional diode may be used |
Answer» D. only an additional diode may be used | |
325. |
A major advantage of DTL over the earlier resistor–transistor logic is the |
A. | increased fan out |
B. | increased fan in |
C. | decreased fan out |
D. | decreased fan in |
Answer» C. decreased fan out | |
326. |
The process to avoid saturating the switching transistor is performed by |
A. | baker clamp |
B. | james r. biard |
C. | chris brown |
D. | totem-pole |
Answer» B. james r. biard | |
327. |
The way to speed up DTL is to add an across intermediate resister is |
A. | small “speed-up†capacitor |
B. | large “speed-up†capacitor |
C. | small “speed-up†transistor |
D. | large †speed-up†transistor |
Answer» B. large “speed-up†capacitor | |
328. |
The full form of CTDL is |
A. | complemented transistor diode logic |
B. | complemented transistor direct logic |
C. | complementary transistor diode logic |
D. | complementary transistor direct logic |
Answer» B. complemented transistor direct logic | |
329. |
The DTL propagation delay is relatively |
A. | large |
B. | small |
C. | moderate |
D. | negligible |
Answer» B. small | |
330. |
How many stages a DTL consist of? |
A. | 2 |
B. | 3 |
C. | 4 |
D. | 5 |
Answer» C. 4 | |
331. |
In DTL amplifying function is performed by |
A. | diode |
B. | transistor |
C. | inductor |
D. | capacitor |
Answer» C. inductor | |
332. |
In DTL logic gating function is performed by |
A. | diode |
B. | transistor |
C. | inductor |
D. | capacitor |
Answer» B. transistor | |
333. |
Diode–transistor logic (DTL) is the direct ancestor of |
A. | register-transistor logic |
B. | transistor–transistor logic |
C. | high threshold logic |
D. | emitter coupled logic |
Answer» C. high threshold logic | |
334. |
The minimum number of transistors can be used by 2 input AND gate is |
A. | 2 |
B. | 3 |
C. | 4 |
D. | 5 |
Answer» B. 3 | |
335. |
TTL circuits with “totem-pole†output stage minimize |
A. | the power dissipation in rtl |
B. | the time consumption in rtl |
C. | the speed of transferring rate in rtl |
D. | propagation delay in rtl |
Answer» B. the time consumption in rtl | |
336. |
The disadvantage of RTL is that |
A. | it uses a maximum number of resistors |
B. | it results in high power dissipation |
C. | high noise creation |
D. | it uses minimum number of transistors |
Answer» C. high noise creation | |
337. |
The limitations of the one transistor RTL NOR gate are overcome by |
A. | two-transistor rtl implementation |
B. | three-transistor rtl implementation |
C. | multi-transistor rtl implementation |
D. | four-transistor rtl implementation |
Answer» D. four-transistor rtl implementation | |
338. |
The primary advantage of RTL technology was that |
A. | it results as low power dissipation |
B. | it uses a minimum number of resistors |
C. | it uses a minimum number of transistors |
D. | it operates swiftly |
Answer» D. it operates swiftly | |
339. |
The role of the is to convert the collector current into a voltage in RTL. |
A. | collector resistor |
B. | base resistor |
C. | capacitor |
D. | inductor |
Answer» B. base resistor | |
340. |
All input of NOR as low produces result as |
A. | low |
B. | mid |
C. | high |
D. | floating |
Answer» D. floating | |
341. |
Simulator enters in which phase after the initialization phase? |
A. | execution phase |
B. | compilation phase |
C. | elaboration phase |
D. | simulation phase |
Answer» B. compilation phase | |
342. |
Hold time is the time needed for the data to after the edge of the clock is triggered. |
A. | decrease |
B. | increase |
C. | remain constant |
D. | negate |
Answer» D. negate | |
343. |
Which of the following tool performs logic optimization? |
A. | simulation tool |
B. | synthesis tool |
C. | routing tool |
D. | rtl compiler |
Answer» C. routing tool | |
344. |
In RTL NOR gate, the output is at logic 1 only when all the inputs are at |
A. | logic 0 |
B. | logic 1 |
C. | +10v |
D. | floating |
Answer» B. logic 1 | |
345. |
Which flip-flop is usually used in the implementation of the registers? |
A. | d flip-flop |
B. | s-r flip-flop |
C. | t flip-flop |
D. | j-k flip-flop |
Answer» B. s-r flip-flop | |
346. |
RTL mainly focuses on describing the flow of signals between |
A. | logic gates |
B. | registers |
C. | clock |
D. | inverter |
Answer» C. clock | |
347. |
RTL is used in HDL to create what level of representations in the circuit? |
A. | high-level |
B. | low-level |
C. | mid-level |
D. | same level |
Answer» B. low-level | |
348. |
RTL is a design abstraction of what kind of circuit? |
A. | asynchronous digital circuit |
B. | synchronous digital circuit |
C. | asynchronous sequential circuit |
D. | analog circuit |
Answer» C. asynchronous sequential circuit | |
349. |
What does RTL in digital circuit design stand for? |
A. | register transfer language |
B. | register transfer logic |
C. | register transfer level |
D. | resistor-transistor logic |
Answer» D. resistor-transistor logic | |
350. |
The quantity of double word is |
A. | 16 bits |
B. | 32 bits |
C. | 4 bits |
D. | 8 bits |
Answer» C. 4 bits | |