MCQOPTIONS
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MCQOPTIONS
This section includes 35 Mcqs, each offering curated multiple-choice questions to sharpen your Electrical Engineering Questions knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Which type of CPLD packaging can provide maximum number of pins on the package due to small size of the pins ? |
| A. | PLCC |
| B. | QFP |
| C. | PGA |
| D. | BGA |
| Answer» E. | |
| 2. |
Which mechanism allocates the binary value to the states in order to reduce the cost of the combinational circuits ? |
| A. | State Reduction |
| B. | State Minimization |
| C. | State Assignment |
| D. | State Evaluation |
| Answer» D. State Evaluation | |
| 3. |
Which is the correct order of sequence for representing the input values in K-map ? |
| A. | (00, 01, 10, 11) |
| B. | (00, 10, 01, 11) |
| C. | (00, 01, 11, 10) |
| D. | (00, 10, 11, 01) |
| Answer» B. (00, 10, 01, 11) | |
| 4. |
When an input signal 1 is applied to a NOT gate, the output is ______________? |
| A. | 0 |
| B. | 1 |
| C. | Either 0 & 1 |
| D. | None of the above |
| Answer» B. 1 | |
| 5. |
What would happen, if smaller logic modules are utilized for performing logical functions associated with FPGA? A. Propagation delay will increase B. FPGA area will increase C. Wastage of logic modules will not be prevented D. Number of interconnected paths in device will decrease ? |
| A. | A & B |
| B. | C & D |
| C. | A & D |
| D. | B & C |
| Answer» B. C & D | |
| 6. |
What is/are the configurable functions of each and every IOBs connected around the FPGA device from the operational point of view ? |
| A. | Input operation |
| B. | Tristate output operation |
| C. | Bi-directional I/O pin access |
| D. | All of the above |
| Answer» E. | |
| 7. |
What is the octal equivalent of the binary number : 10111101 ? |
| A. | 675 |
| B. | 275 |
| C. | 572 |
| D. | 573 |
| Answer» C. 572 | |
| 8. |
The universal gate is ________________? |
| A. | NAND gate |
| B. | OR gate |
| C. | AND gate |
| D. | None of the above |
| Answer» B. OR gate | |
| 9. |
The only function of NOT gate is to__________________? |
| A. | Stop signal |
| B. | Invert input signal |
| C. | Act as a universal gate |
| D. | None of the above |
| Answer» C. Act as a universal gate | |
| 10. |
The number of Boolean functions that can be generated by n variables is equal to_________________? |
| A. | 2n |
| B. | 22 n |
| C. | 2n-1 |
| D. | — 2n |
| Answer» C. 2n-1 | |
| 11. |
The number 1000 would appear just immediately after__________________? |
| A. | FFFF (hex) |
| B. | 1111 (binary) |
| C. | 7777 (octal) |
| D. | All of the above |
| Answer» B. 1111 (binary) | |
| 12. |
The NOR gate is OR gate followed by____________________? |
| A. | AND gate |
| B. | NAND gate |
| C. | NOT gate |
| D. | None of the above |
| Answer» D. None of the above | |
| 13. |
The NAND gate is AND gate followed by_________________? |
| A. | NOT gate |
| B. | OR gate |
| C. | AND gate |
| D. | None of the above |
| Answer» B. OR gate | |
| 14. |
The inverter is _________________? |
| A. | NOT gate |
| B. | OR gate |
| C. | AND gate |
| D. | None of the above |
| Answer» B. OR gate | |
| 15. |
The inputs of a NAND gate are connected together. The resulting circuit is _______________? |
| A. | OR gate |
| B. | AND gate |
| C. | NOT gate |
| D. | None of the above |
| Answer» D. None of the above | |
| 16. |
The fan put of a 7400 NAND gate is_______________? |
| A. | 2TTL |
| B. | 5TTL |
| C. | 8TTL |
| D. | 10TTL |
| Answer» E. | |
| 17. |
The binary number 10101 is equivalent to decimal number_________________? |
| A. | 19 |
| B. | 12 |
| C. | 27 |
| D. | 21 |
| Answer» E. | |
| 18. |
The binary code of (21.125)10 is_______________? |
| A. | 10101.001 |
| B. | 10100.001 |
| C. | 10101.010 |
| D. | 10100.111 |
| Answer» B. 10100.001 | |
| 19. |
Positive logic in a logic circuit is one in which______________? |
| A. | logic 0 and 1 are represented by 0 and positive voltage respectively |
| B. | logic 0 and, -1 are represented by negative and positive voltages respectively |
| C. | logic 0 voltage level is higher than logic 1 voltage level |
| D. | logic 0 voltage level is lower than logic 1 voltage level |
| Answer» E. | |
| 20. |
NAND gates are preferred over others because these__________________? |
| A. | have lower fabrication area |
| B. | can be used to make any gate |
| C. | consume least electronic power |
| D. | provide maximum density in a chip |
| Answer» C. consume least electronic power | |
| 21. |
Most of the digital computers do not have floating point hardware because_____________? |
| A. | floating point hardware is costly |
| B. | it is slower than software |
| C. | it is not possible to perform floating point addition by hardware |
| D. | of no specific reason. |
| Answer» B. it is slower than software | |
| 22. |
Indicate which of the following three binary additions are correct? 1.1011 + 1010 = 10101 II. 1010 + 1101 = 10111 ?_x005F_x000D_III. 1010 + 1101 = 11111 |
| A. | I and II |
| B. | II and III |
| C. | III only |
| D. | II and III |
| Answer» B. II and III | |
| 23. |
In which of the following base systems is 123 not a valid number ? |
| A. | Base 10 |
| B. | Base 16 |
| C. | Base8 |
| D. | Base 3 |
| Answer» E. | |
| 24. |
In case of OR gate, no matter what the number of inputs, a____________________? |
| A. | 1 at any input causes the output to be at logic 1 |
| B. | 1 at any input causes the output to be at logic 0 |
| C. | 0 any input causes the output to be at logic 0 |
| D. | 0 at any input causes the output to be at logic 1 |
| Answer» B. 1 at any input causes the output to be at logic 0 | |
| 25. |
In Boolean algebra, the bar sign (-) indicates__________________? |
| A. | OR operation |
| B. | AND operation |
| C. | NOT operation |
| D. | None of the above |
| Answer» D. None of the above | |
| 26. |
Excess-3 code is known as_________________? |
| A. | Weighted code |
| B. | Cyclic redundancy code |
| C. | Self-complementing code |
| D. | Algebraic code |
| Answer» D. Algebraic code | |
| 27. |
Digital computers are more widely used as compared to analog computers, because they are______________? |
| A. | less expensive |
| B. | always more accurate and faster |
| C. | useful over wider ranges of problem types |
| D. | easier to maintain |
| Answer» D. easier to maintain | |
| 28. |
Digital circuit can be made by the repeated use of________________? |
| A. | OR gates |
| B. | NOT gates |
| C. | NAND gates |
| D. | None of the above |
| Answer» D. None of the above | |
| 29. |
Consider the representation of six-bit numbers by two’s complement, one’s complement, or by sign and magnitude: In which representation is there overflow from the addition of the integers 011000 and 011000 ? |
| A. | Two’s complement only |
| B. | Sign and magnitude and one’s complement only |
| C. | Two’s complement and one’s complement only |
| D. | All three representations |
| Answer» E. | |
| 30. |
Assuming 8 bits for data, 1 bit for parity, I start bit and 2 stop bits, the number of characters that 1200 BPS communication line can transmit is__________________? |
| A. | 10 CPS |
| B. | 120 CPS |
| C. | 12CPS |
| D. | None of the above |
| Answer» D. None of the above | |
| 31. |
An OR gate has 6 inputs. The number of input words in its truth table are________________? |
| A. | 6 |
| B. | 32 |
| C. | 64 |
| D. | 128 |
| Answer» D. 128 | |
| 32. |
An AND gate will function as OR if________________? |
| A. | all the inputs to the gates are “1” |
| B. | all the inputs are ‘0’ |
| C. | either of the inputs is “1” |
| D. | all the inputs and outputs are complemented |
| Answer» E. | |
| 33. |
Among the logic families, the family which can be used at very high frequency greater than 100 MHz in a 4 bit synchronous counter is__________________? |
| A. | TTLAS |
| B. | CMOS |
| C. | ECL |
| D. | TTLLS |
| Answer» D. TTLLS | |
| 34. |
A NAND gate is called a universal logic element because______________? |
| A. | it is used by everybody |
| B. | any logic function can be realized by NAND gates alone |
| C. | all the minization techniques are applicable for optimum NAND gate realization |
| D. | many digital computers use NAND gates |
| Answer» C. all the minization techniques are applicable for optimum NAND gate realization | |
| 35. |
A debouncing circuit is________________? |
| A. | an astable MV |
| B. | a bistable MV |
| C. | a latch |
| D. | a monostable MV |
| Answer» D. a monostable MV | |