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MCQOPTIONS
This section includes 646 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Consider the representation of six-bit numbers by two s complement, one scomplement, or by sign and magnitude: In which representation is there overflow fromthe addition of the integers 011000 and 011000? |
| A. | two s complement only |
| B. | sign and magnitude and one s complement only |
| C. | two s complement and one s complement only |
| D. | all three representa tions. |
| Answer» E. | |
| 2. |
Indicate which of the following three binary additions are correct? 1.1011 + 1010 = 10101II. 1010 + 1101 = 10111III. 1010 + 1101 = 11111 |
| A. | i and ii |
| B. | ii and iii |
| C. | iii only |
| D. | ii and i |
| Answer» E. | |
| 3. |
Minimise the logic function (POS Form) F A,B,C,D) = PI M (1, 2, 3, 8, 9, 10, 11,14) d (7, 15) |
| A. | f=[(b+d )+(b+ c ) (a +c )+(a +b)] |
| B. | f=[(b+d )+(b +c ) ( a +c )+ (a +b)] |
| C. | f=[(b+d )+(b +c ) ( a +c )+ (a +b)] |
| D. | f=[(b+d )+ (b+c ) ( a +c )+(a +b )] |
| Answer» B. f=[(b+d )+(b +c ) ( a +c )+ (a +b)] | |
| 4. |
If the region beneath the gate is left initially uncharged the gate field must induce achannel before current can flow. Thus the gate voltage enhances thechannel current and sucha device is said to operate in the |
| A. | depletion mode operation mos |
| B. | enhancemen t mode operation of mos |
| C. | both mode |
| D. | none of this |
| Answer» C. both mode | |
| 5. |
THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUTMULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT GATE |
| A. | and |
| B. | or |
| C. | nand |
| D. | xor |
| Answer» C. nand | |
| 6. |
Consider an up/down counter that counts between 0 and 15, if external input(X) is 0 the counter counts upward (0000 to 1111) and if external input (X) is 1 the counter counts downward (1111 to 0000), now suppose that the present state is 1100 and X=1, the next state of the counter will be |
| A. | 0 |
| B. | 1101 |
| C. | 1011 |
| D. | 1111 |
| Answer» D. 1111 | |
| 7. |
In the following question, match each of the items A, B and C on the left with an approximation item on the rightA. Shift register can be used 1. for code conversionB. A multiplexer can be used 2. to generate memory slipto selectC. A decoder can be used 3. for parallel to serial conversion4. as many to one switch5. for analog to digital conversion |
| A. | a b c 1 2 3 |
| B. | a b c 3 4 1 |
| C. | a b c 5 4 2 |
| D. | a b c 1 3 5 |
| Answer» C. a b c 5 4 2 | |
| 8. |
occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay |
| A. | race condition |
| B. | clock skew |
| C. | ripple effect |
| D. | none of given options |
| Answer» C. ripple effect | |
| 9. |
A 8-bit serial in / parallel out shift register contains the value 8 , clock signal(s) will be required to shift the value completely out of the register. |
| A. | 1 |
| B. | 2 |
| C. | 4 |
| D. | 8 |
| Answer» E. | |
| 10. |
In Q output of the last flip-flop of the shift register is connected to the data input of the firstflip-flop of the shift register. |
| A. | moore machine |
| B. | meally machine |
| C. | johnson counter |
| D. | ring counter |
| Answer» E. | |
| 11. |
In an odd-parity system, the data that will produce a parity bit = 1 is . |
| A. | data = 1010011 |
| B. | data = 1111000 |
| C. | data = 1100000 |
| D. | all of the above |
| Answer» E. | |
| 12. |
AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS 1 . WHAT WILL BE THE VALUE OF REGISTER AFTER THREE CLOCK PULSES? |
| A. | 2 |
| B. | 4 |
| C. | 6 |
| D. | 8 |
| Answer» E. | |
| 13. |
Match List I with List II and select the correct answer form the codes given below the list List IA. A shift register can beB. A multiplexerC. A decoder can List II 1.for parallel to serial conversion2.to generate memory can be used chip select 3.for parallel to serial conversionCODES: A B C |
| A. | 3 1 2 |
| B. | 2 3 1 |
| C. | 1 3 2 |
| D. | 1 2 3 |
| Answer» D. 1 2 3 | |
| 14. |
occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. |
| A. | race condition |
| B. | clock skew |
| C. | ripple effect |
| D. | none of given options |
| Answer» C. ripple effect | |
| 15. |
To subtract a signed number (the subtrahend) from another signed number (the minuend) in the 2's complement system, the minuend is . |
| A. | complemented only if it is positive |
| B. | complemente d only if it is negative |
| C. | always complemente d |
| D. | never compleme nted |
| Answer» E. | |
| 16. |
A 8-bit serial in / parallel out shift register contains the value “8”, clock signal(s) will be required to shift the value completely out of the register. |
| A. | 1 |
| B. | 2 |
| C. | 4 |
| D. | 8 |
| Answer» E. | |
| 17. |
We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZand 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by |
| A. | using s-r flop- flop |
| B. | d-flipflop |
| C. | j-k flip-flop |
| D. | t-flip-flop |
| Answer» D. t-flip-flop | |
| 18. |
In an odd-parity system, the data that will produce a parity bit = 1 is . |
| A. | data = 1010011 |
| B. | data = 1111000 |
| C. | data = 1100000 |
| D. | all of the above |
| Answer» E. | |
| 19. |
Q2 :=Q1 OR X OR Q3The above ABEL expression will be |
| A. | q2:= q1 $ x $ q3 |
| B. | q2:= q1 # x# q3 |
| C. | q2:= q1 & x& q3 |
| D. | q2:= q1 ! x ! q3 |
| Answer» C. q2:= q1 & x& q3 | |
| 20. |
Minimise the logic function (POS Form) F A,B,C,D) = PI M (1, 2, 3, 8, 9,10, 11,14)× d (7, 15) |
| A. | f=[(b+d’)+(b+ c’)’(a’+c’)+(a’+b)]’ |
| B. | f=[(b+d’)+(b+c’)’(‘a’+c’)+ (a’+b)]’ |
| C. | f=[(b+d’)+(b+c’)’(‘a’+c’)+ (a’+b)]’ |
| D. | f=[(b+d’)+ (b+c’)’(‘a’+c’)+(a’+b)]’ |
| Answer» B. f=[(b+d’)+(b+c’)’(‘a’+c’)+ (a’+b)]’ | |
| 21. |
To subtract a signed number (the subtrahend) from another signed number (the minuend) in the 2's complement system, the minuend is . |
| A. | complemented only if it is positive |
| B. | complemente d only if it is negative |
| C. | always complemente d |
| D. | never compleme nted |
| Answer» E. | |
| 22. |
AB+(A+B)’ is equivalent to |
| A. | a ex-nor b |
| B. | a ex or b |
| C. | (a+b)a |
| D. | (a+b)b |
| Answer» B. a ex or b | |
| 23. |
1. Open collector output 2. Totem-Pole Output 3. Tri-state output are thetype of |
| A. | ttl logic |
| B. | rtl logic |
| C. | cmos logic |
| D. | none ofthis |
| Answer» B. rtl logic | |
| 24. |
The rise time (tr) is the time it takes for a pulse to rise from its point up to its point. The fall time (tf) is the length of time it takes to fall from the to the point. |
| A. | 10%, 90%,90%, 10% |
| B. | 90%, 10%,10%, 90% |
| C. | 20%, 80%,80%, 20% |
| D. | 10%,70.7%,70.7%,10% |
| Answer» B. 90%, 10%,10%, 90% | |
| 25. |
If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch willbe |
| A. | set |
| B. | reset |
| C. | invalid |
| D. | clear |
| Answer» B. reset | |
| 26. |
Perform 2’s complement subtraction of (7)10 − (11)10 . |
| A. | 1100 (or -4) |
| B. | 1101 (or -5) |
| C. | 1011 (or -3) |
| D. | 1110 (or-6) |
| Answer» B. 1101 (or -5) | |
| 27. |
Except for , STD_LOGIC may have the following values. |
| A. | \z\ |
| B. | \u\ |
| C. | \?\ |
| D. | \l\ |
| Answer» D. \l\ | |
| 28. |
The nominal value of the dc supply voltage for TTL (transistor-transistorlogic) devices is |
| A. | 0v |
| B. | 5v |
| C. | 10v |
| D. | 15v |
| Answer» C. 10v | |
| 29. |
A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and theresulting output of each value. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 30. |
Two 4-bit comparators are cascaded to form an 8-bit comparator. The cascading inputs of the most significant 4 bits should be connected. |
| A. | to the outputs from the least significant 4- bit comparator |
| B. | to the cascading inputs of the least significant 4- bit comparator |
| C. | a = b to a logic high, a< b and a > b to a logic low |
| D. | ground |
| Answer» B. to the cascading inputs of the least significant 4- bit comparator | |
| 31. |
Excess-8 code assigns to “-8” |
| A. | 1110 |
| B. | 1100 |
| C. | 1000 |
| Answer» E. | |
| 32. |
Perform following subtraction(ii) 11011-11001 using 2’s complement |
| A. | 10 |
| B. | 111 |
| C. | 11 |
| D. | 10011 |
| Answer» B. 111 | |
| 33. |
Perform following subtraction (i) 11001-10110 using 1’s complement |
| A. | 11 |
| B. | 111 |
| C. | 10 |
| D. | 10011 |
| Answer» B. 111 | |
| 34. |
AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT WILL BE THE VALUE OFREGISTER AFTER THREE CLOCK PULSES? |
| A. | 2 |
| B. | 4 |
| C. | 6 |
| D. | 8 |
| Answer» E. | |
| 35. |
Consider the representation of six-bit numbers by two’s complement, one’scomplement, or by sign and magnitude: In which representation is there overflow fromthe addition of the integers 011000 and 011000? |
| A. | two’s complement only |
| B. | sign and magnitude and one’s complement only |
| C. | two’s complement and one’s complement only |
| D. | all three representa tions. |
| Answer» E. | |
| 36. |
ECL IC technology is……………….than TTL technology. |
| A. | faster |
| B. | slower |
| C. | equal |
| D. | none of this |
| Answer» B. slower | |
| 37. |
A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 iswaiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing . |
| A. | 1110 |
| B. | 111 |
| C. | 1000 |
| D. | 1001 |
| Answer» E. | |
| 38. |
Perform the following subtractions using 2’s complement method. 01000 – 01001 |
| A. | 1 |
| B. | 10 |
| C. | 11 |
| D. | 11110 |
| Answer» B. 10 | |
| 39. |
What is the minimum number of 2 input NAND gates required to implement the functionF = (x'+y') (z+w) |
| A. | 6 |
| B. | 5 |
| C. | 4 |
| D. | 3 |
| Answer» D. 3 | |
| 40. |
is used to simplify the circuit that determines the next state. |
| A. | state diagram |
| B. | next state table |
| C. | state reduction |
| D. | state assignmen t |
| Answer» E. | |
| 41. |
The device shown here is most likely a . |
| A. | comparator |
| B. | multiplexer |
| C. | demultiplexe r |
| D. | parity generator |
| Answer» D. parity generator | |
| 42. |
Conversion of fractional number 0.6875 into its equivalent binarynumber: |
| A. | 0.1011 |
| B. | 0.1111 |
| C. | 0.10111 |
| D. | 0.0101 |
| Answer» B. 0.1111 | |
| 43. |
A full-adder has a Cin = 0. What are the sum and the carry (Cout) when A= 1 and B = 1? |
| A. | 0 |
| B. | 0 |
| C. | 0 |
| D. | 0 |
| Answer» C. 0 | |
| 44. |
The 2’s complement of the number 1101110 is |
| A. | 10001 |
| B. | 10001 |
| C. | 10010 |
| D. | none |
| Answer» D. none | |
| 45. |
A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BYTHE MANUFACTURER. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 46. |
occurs when the same clock signal arrives at different times at different clock inputs due topropagation delay |
| A. | race condition |
| B. | clock skew |
| C. | ripple effect |
| D. | none of given options |
| Answer» C. ripple effect | |
| 47. |
A 8-bit serial in / parallel out shift register contains the value “8”, clock signal(s) will be required to shiftthe value completely out of the register. |
| A. | 1 |
| B. | 2 |
| C. | 4 |
| D. | 8 |
| Answer» E. | |
| 48. |
If the region beneath the gate is left initially uncharged the gate field must induce achannel before current can flow. Thus the gate voltage enhances thechannel current and sucha device is said to operate in the |
| A. | depletion mode operation mos |
| B. | enhancemen t mode operation ofmos |
| C. | both mode |
| D. | none of this |
| Answer» C. both mode | |
| 49. |
A full-adder has a Cin = 0. What are the sum ( ) and the carry (Cout)when A = 1 and B = 1? |
| A. | 0 |
| B. | 0 |
| C. | = 1, cout = 0 |
| D. | = 1, cout= 1 |
| Answer» C. = 1, cout = 0 | |
| 50. |
12-bit 2’s complement of –73.75 is |
| A. | 01001001.1100 |
| B. | 11001001.1100 |
| C. | 10110110.0100 |
| D. | 10110110.1100 |
| Answer» D. 10110110.1100 | |