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MCQOPTIONS
This section includes 2291 Mcqs, each offering curated multiple-choice questions to sharpen your Engineering knowledge and support exam preparation. Choose a topic below to get started.
| 651. |
Which of the following statements will add the accumulator and register 3? |
| A. | ADD @R3, @A |
| B. | ADD @A, R3 |
| C. | ADD R3, A |
| D. | ADD A, R3 |
| Answer» E. | |
| 652. |
Data transfer from I/O to external data memory can only be done with the MOV command. |
| A. | True |
| B. | False |
| Answer» C. | |
| 653. |
Which of the following commands will move the number 27H into the accumulator? |
| A. | MOV A, P27 |
| B. | MOV A, #27H |
| C. | MOV A, 27H |
| D. | MOV A, @27 |
| Answer» C. MOV A, 27H | |
| 654. |
Which mode of operation is being used when a 555 timer chip has two external resistors and an external capacitor? |
| A. | monostable |
| B. | pulse stretching |
| C. | Schmitt triggering |
| D. | astable |
| Answer» E. | |
| 655. |
What is the duty cycle of the waveform at the output of the circuit given below? |
| A. | 78% |
| B. | 56% |
| C. | 50% |
| D. | 44% |
| Answer» C. 50% | |
| 656. |
The monostable multivibrator circuit is not an oscillator because ________. |
| A. | its output switches between two states |
| B. | it requires a trigger to obtain an output signal |
| C. | it requires a sine wave input signal |
| D. | the circuit does not require a dc power supply |
| Answer» C. it requires a sine wave input signal | |
| 657. |
A retriggerable one shot has a pulse of 10 ms. 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ ms. |
| A. | 3 |
| B. | 7 |
| C. | 10 |
| D. | 13 |
| Answer» E. | |
| 658. |
Is the circuit given below an astable multivibrator or a monostable multivibrator? |
| A. | monostable |
| B. | astable |
| Answer» B. astable | |
| 659. |
What is the difference between a retriggerable one shot and a nonretriggerable one shot? |
| A. | The nonretriggerable can only be triggered once. |
| B. | The retriggerable can be triggered many times. |
| C. | The output pulse can be stretched with a nonretriggerable. |
| D. | The output pulse can be stretched with a retriggerable. |
| Answer» E. | |
| 660. |
Triggering a retriggerable one shot during pulse generation will: |
| A. | time out the original pulse |
| B. | extend the pulse to this trigger width |
| C. | have no effect |
| D. | double the original pulse width |
| Answer» C. have no effect | |
| 661. |
Which is not a MOSFET terminal? |
| A. | Gate |
| B. | Drain |
| C. | Source |
| D. | Base |
| Answer» E. | |
| 662. |
For a CMOS gate, which is the best speed-power product? |
| A. | 1.4 pJ |
| B. | 1.6 pJ |
| C. | 2.4 pJ |
| D. | 3.3 pJ |
| Answer» B. 1.6 pJ | |
| 663. |
Which transistor element is used in CMOS logic? |
| A. | FET |
| B. | MOSFET |
| C. | Bipolar |
| D. | Unijunction |
| Answer» C. Bipolar | |
| 664. |
The greater the propagation delay, the ________. |
| A. | lower the maximum frequency |
| B. | higher the maximum frequency |
| C. | maximum frequency is unaffected |
| D. | minimum frequency is unaffected |
| Answer» B. higher the maximum frequency | |
| 665. |
PMOS and NMOS circuits are used largely in ________. |
| A. | MSI functions |
| B. | LSI functions |
| C. | diode functions |
| D. | TTL functions |
| Answer» C. diode functions | |
| 666. |
If ICCH is specified as 1.1 mA when VCC is 5 V and if the gate is in a static (noncharging) HIGH output state, the power dissipation (PD) of the gate is ________. |
| A. | 5.5 mW |
| B. | 5.5 W |
| C. | 5 mW |
| D. | 1.1 mW |
| Answer» B. 5.5 W | |
| 667. |
It is best not to leave unused TTL inputs unconnected (open) because of TTL's ________. |
| A. | noise sensitivity |
| B. | low-current requirement |
| C. | open-collector outputs |
| D. | tristate construction |
| Answer» B. low-current requirement | |
| 668. |
Which is not an output state for tristate logic? |
| A. | HIGH |
| B. | LOW |
| C. | High-Z |
| D. | Low-Z |
| Answer» E. | |
| 669. |
Why is a binary-weighted DAC usually limited to 4-bit binary conversion? |
| A. | too many pins on the IC |
| B. | too many op amps needed |
| C. | too many different values of capacitors |
| D. | too many different values of resistors |
| Answer» E. | |
| 670. |
What is gain error in a DAC? |
| A. | missing codes |
| B. | error in the slope of the output staircase waveform |
| C. | more or less input voltage is required for the first step than what is specified |
| Answer» C. more or less input voltage is required for the first step than what is specified | |
| 671. |
An actuator is usually a device that: |
| A. | converts analog data to meaningful digital data. |
| B. | controls a physical variable. |
| C. | stores digital data and then processes that data according to a set of specified instructions. |
| D. | converts a physical variable to an electrical variable. |
| Answer» C. stores digital data and then processes that data according to a set of specified instructions. | |
| 672. |
The primary disadvantage of the simultaneous A/D converter is: |
| A. | that it requires the input voltage to be applied to the inputs simultaneously |
| B. | the long conversion time required |
| C. | the large number of output lines required to simultaneously decode the input voltage |
| D. | the large number of comparators required to represent a reasonable sized binary number |
| Answer» E. | |
| 673. |
What is the output voltage for the circuit shown below? |
| A. | 10 V |
| B. | 20 V |
| C. | 30 V |
| D. | 40 V |
| Answer» D. 40 V | |
| 674. |
What is the main disadvantage of the counter-ramp A/D converter? |
| A. | It requires a counter. |
| B. | The counter must count up from zero at the beginning of each conversion sequence, and the conversion time will vary depending on the input voltage. |
| C. | It requires a precision clock in order for the conversion to be reliable. |
| D. | The counter must count up from zero at the beginning of each conversion sequence, and the conversion time will vary depending on the input voltage. It requires a precision clock in order for the conversion to be reliable. |
| Answer» C. It requires a precision clock in order for the conversion to be reliable. | |
| 675. |
Referring to the given figure, what appears to be wrong, if anything, with the output of the D/A converter? |
| A. | The input signal is probably noisy. |
| B. | There appears to be some nonlinearity in the scope display. |
| C. | The converter has a nonmonotonic output error. |
| D. | It appears that certain input codes are incorrect; double-check the input coding. |
| Answer» D. It appears that certain input codes are incorrect; double-check the input coding. | |
| 676. |
What is the maximum conversion time for a counter-ramp ADC with 8-bit resolution and a clock frequency of 20 kHz? |
| A. | 12.8 ms |
| B. | 6.4 ms |
| C. | 0.05 ms |
| D. | 0.4 ms |
| Answer» B. 6.4 ms | |
| 677. |
A test system using the GPIB is being used to monitor a potentially dangerous crash test from a distance of 200 feet. The engineer decides to have you fabricate a special cable, rather than order one, since all the materials are on hand and the tests are already behind schedule. When the tests are run, the test system is erratic and the data is almost useless. What has gone wrong? |
| A. | The engineer is probably not using the correct data format for the specific instruments being used to collect the data. |
| B. | The GPIB cable is too long; a bus extender should be used. |
| C. | The cable should be shielded and properly grounded. |
| D. | The tests themselves probably produced extraneous signals that confused the instruments, resulting in unusable data. |
| Answer» C. The cable should be shielded and properly grounded. | |
| 678. |
A certain digital-to-analog converter has a step size of 0.25 V and a full-scale output of 7.75 V. Determine the percent of resolution and the number of input binary bits. |
| A. | 31%, 4 bits |
| B. | 3.23%, 4 bits |
| C. | 31%, 5 bits |
| D. | 3.23%, 5 bits |
| Answer» E. | |
| 679. |
What is one advantage to using a parallel-encoded (flash) ADC? |
| A. | less expensive |
| B. | very fast conversion |
| C. | less complicated circuit |
| Answer» C. less complicated circuit | |
| 680. |
If the same analog signal is to be converted to an 8-bit resolution using a counter-ramp ADC, how many comparator circuits would be used? |
| A. | 1 |
| B. | 8 |
| C. | 127 |
| D. | 255 |
| Answer» B. 8 | |
| 681. |
What is the major advantage of the R/2R ladder D/A converter as compared to a binary-weighted D/A converter? |
| A. | It has fewer parts for the same number of inputs. |
| B. | It is much easier to analyze its operation. |
| C. | It uses only two different resistor values. |
| D. | The virtual ground is eliminated and the circuit is therefore easier to understand and troubleshoot. |
| Answer» D. The virtual ground is eliminated and the circuit is therefore easier to understand and troubleshoot. | |
| 682. |
What is the main disadvantage of the stairstep-ramp A/D converter? |
| A. | The counter must count up from zero at the beginning of each conversion sequence, and the conversion time will vary depending on the input voltage. |
| B. | It requires a counter. |
| C. | It requires a precision clock in order for the conversion to be reliable. |
| D. | All of the above |
| Answer» B. It requires a counter. | |
| 683. |
What is the purpose of a sample-and-hold circuit? |
| A. | To keep temporary memory |
| B. | To hold a voltage constant so an ADC has time to produce an output |
| C. | To hold a voltage constant so a DAC has time to produce an output |
| D. | To hold data after a multiplexer has selected an output |
| Answer» C. To hold a voltage constant so a DAC has time to produce an output | |
| 684. |
What function is performed by the block labeled X in the given figure? |
| A. | Analog-to-digital conversion |
| B. | Digital-to-analog conversion |
| C. | Audio ON/OFF control |
| D. | Power supply for the audio amplifier |
| Answer» C. Audio ON/OFF control | |
| 685. |
Inaccurate A/D conversion may be due to: |
| A. | constant analog input voltage |
| B. | linear ramp usage |
| C. | intermittent counter inputs |
| D. | faulty sample-and-hold circuitry |
| Answer» E. | |
| 686. |
What circuitry is on an ADC0808 IC? |
| A. | A multiplexer |
| B. | An ADC |
| C. | A 3-bit select input code |
| D. | All of the above |
| Answer» E. | |
| 687. |
What is the maximum conversion time for an 8-bit successive-approximation ADC with a clock frequency of 20 kHz? |
| A. | 12.8 ms |
| B. | 6.4 ms |
| C. | 0.05 ms |
| D. | 0.4 ms |
| Answer» E. | |
| 688. |
When comparing the conversions from digital-to-analog and analog-to-digital, the A/D conversion is generally: |
| A. | less complicated but more time consuming than the D/A conversion. |
| B. | more complicated and more time consuming than the D/A conversion. |
| C. | less complicated and less time consuming than the D/A conversion. |
| D. | more complicated but less time consuming than the D/A conversion. |
| Answer» C. less complicated and less time consuming than the D/A conversion. | |
| 689. |
Which of the statements below best describes the basic operation of a dual-slope A/D converter? |
| A. | The input voltage is used to set the frequency of a voltage-controlled oscillator (VCO). The VCO quits changing frequency when the input voltage stabilizes. The frequency of the VCO, which is proportional to the analog input voltage, is measured and is displayed on the digital display as a voltage reading. |
| B. | A ramp generator is used to enable a counter through a comparator. When the ramp voltage equals the input voltage, the counter is latched and then reset. The counter reading is proportional to the input voltage since the ramp is changing at a constant V/second rate. |
| C. | A ramp voltage and analog input voltage are applied to a comparator. As the input voltage causes the integrating capacitor to charge, it will at some point equal the ramp voltage. The ramp voltage is measured and displayed on the digital panel meter. |
| D. | Two ramps are generated: one by the input voltage and the other by a reference voltage. The input voltage ramp charges the integrating capacitor, while the reference voltage discharges the capacitor and enables the counter until the capacitor is discharged, at which time the counter value is loaded into the output latches. |
| Answer» E. | |
| 690. |
Referring to the given figure, what appears to be wrong, if anything, with the D/A converter and what should be done to correct the problem? |
| A. | There is nothing wrong with the converter. |
| B. | There is an offset error; if no provision is made for adjusting the offset, the op-amp may need to be changed. |
| C. | There is a nonlinearity error; the op-amp must be changed. |
| D. | The power supply voltage appears to be too high; adjust the power supply to the correct value. |
| Answer» C. There is a nonlinearity error; the op-amp must be changed. | |
| 691. |
What is the major advantage of the R/2R ladder DAC as compared to a binary-weighted-input DAC? |
| A. | It has fewer parts for the same number of inputs. |
| B. | It is much easier to analyze its operation. |
| C. | It uses only two different resistor values. |
| D. | The virtual ground is eliminated and the circuit is therefore easier to understand and troubleshoot. |
| Answer» D. The virtual ground is eliminated and the circuit is therefore easier to understand and troubleshoot. | |
| 692. |
An analog-to-digital converter has a four-bit output. How many analog values can it represent? |
| A. | 4 |
| B. | 1/4 |
| C. | 16 |
| D. | 0.0625 |
| Answer» D. 0.0625 | |
| 693. |
The basic approach to testing D/A converters is to: |
| A. | apply a sequence of binary codes covering the full range of input values to the circuit input while observing the output on an oscilloscope. The output should consist of a linear stairstep ramp. |
| B. | single-step the device through its full input range while checking the output with a DMM. |
| C. | check the output with zero input and then full input. The output of the converter should extend from zero to its maximum value. If so, then everything in between can be assumed to be operating properly. |
| D. | apply the correct input to the analog terminal and then check to see if the proper binary code exists on the digital inputs. |
| Answer» B. single-step the device through its full input range while checking the output with a DMM. | |
| 694. |
What is the maximum output voltage for the circuit shown below? |
| A. | 20 volts |
| B. | 5 volts |
| C. | 9.375 volts |
| D. | 2.1775 volts |
| Answer» D. 2.1775 volts | |
| 695. |
One major difference between a counter-ramp A/D converter and a successive-approximation converter is: |
| A. | the counter-ramp A/D converter is much faster than the successive-approximation converter |
| B. | with the successive-approximation converter the final binary result is always slightly less than the equivalent analog input, whereas with the counter-ramp A/D converter it is slightly more |
| C. | with the successive-approximation converter the final binary result is always slightly more than the equivalent analog input, whereas with the counter-ramp A/D converter it is slightly less |
| D. | none of the above |
| Answer» C. with the successive-approximation converter the final binary result is always slightly more than the equivalent analog input, whereas with the counter-ramp A/D converter it is slightly less | |
| 696. |
What is the resolution of a D/A converter? |
| A. | the comparison between the actual output of the converter and its expected output |
| B. | the reciprocal of the number of discrete steps in the D/A output |
| C. | the deviation between the ideal straight-line output and the actual output of the converter |
| D. | the ability to resolve between forward and reverse steps when sequenced over its entire range |
| Answer» C. the deviation between the ideal straight-line output and the actual output of the converter | |
| 697. |
The process by which a computer acquires digitized analog data is referred to as ________. |
| A. | data acquisition |
| B. | monotonicity |
| C. | analog resolution |
| D. | systematic digital conversion |
| Answer» B. monotonicity | |
| 698. |
What is the output voltage of the given circuit if the inputs are as follows: 20 = 1, 21 = 1, 22 = 0, 23 = 0? |
| A. | 3.115 volts |
| B. | 2.8025 volts |
| C. | 1.875 volts |
| D. | 1.24 volts |
| Answer» D. 1.24 volts | |
| 699. |
The data transmission system shown in below has a problem; the parity error output is always high. A logic analyzer is used to examine the system and shows that the DATA IN on the left matches the DATA OUT on right. What might be causing the problem? |
| A. | The error gate could be defective. |
| B. | The storage circuit could be defective. |
| C. | The parity checker could be bad. |
| D. | Any of the above. |
| Answer» E. | |
| 700. |
The IEEE/ANSI symbol for a decoder has the internal designation bcd/dec. This means the decoder is a: |
| A. | decimal-to-BCD decoder with ten inputs and four outputs. |
| B. | BCD-to-decimal decoder with ten inputs and four outputs. |
| C. | decimal-to-BCD decoder with four inputs and ten outputs. |
| D. | BCD-to-decimal decoder with four inputs and ten outputs. |
| Answer» E. | |