2291 + Mcqs in Digital Electronics McqOptions

1.	Fan-out for a typical TTL gate is ________.
A.	100
B.	54
C.	10
D.	4
Answer» D. 4

Discussion

2.	The time it takes for an input signal to pass through internal circuitry and generate the appropriate output effect is known as ________.
A.	fan-out
B.	propagation delay
C.	rise time
D.	fall time
Answer» C. rise time

Discussion

3.	A pull-down resistor must be used with open-collector TTL circuits.
A.	True
B.	False
Answer» C.

Discussion

4.	The lower transistor of a totem-pole output is saturated when the gate output is ________.
A.	overdriven
B.	HIGH
C.	LOW
D.	malfunctioning
Answer» D. malfunctioning

Discussion

5.	Metal-oxide semiconductor field-effect transistors (MOSFETs) are the active switching elements in CMOS circuits.
A.	True
B.	False
Answer» B. False

Discussion

6.	Totem-pole outputs ________ be connected ________ because ________.
A.	can, in parallel, sometimes higher output current is required
B.	cannot, together, if the outputs are in opposite states excessively high currents can damage one or both of the devices
C.	should, in series, certain applications may require higher output voltage
D.	can, together, together they can handle larger load currents and higher output voltages
Answer» C. should, in series, certain applications may require higher output voltage

Discussion

7.	There are four different logic level ranges for TTL and CMOS: VIL, VIH, VOL, and VOH.
A.	True
B.	False
Answer» B. False

Discussion

8.	Power dissipation is a measure of a circuit's noise immunity.
A.	True
B.	False
Answer» C.

Discussion

9.	The total sink current decreases with an increase in each load gate input.
A.	True
B.	False
Answer» C.

Discussion

10.	The two's-complement method is used in computer systems that perform arithmetic.
A.	True
B.	False
Answer» B. False

Discussion

11.	Digital computers use an easier method to subtract binary numbers, called one's complement.
A.	True
B.	False
Answer» C.

Discussion

12.	Binary multiplication is like decimal multiplication except you deal only with 1s and 0s.
A.	True
B.	False
Answer» B. False

Discussion

13.	The solution to the binary problem 1011 0111 is 1000.
A.	True
B.	False
Answer» C.

Discussion

14.	A 74HC283 can be used to implement a 4-bit full adder.
A.	True
B.	False
Answer» B. False

Discussion

15.	When the 2's-complement system is used, the number to be subtracted is changed to its 2's complement and then added to the minuend.
A.	True
B.	False
Answer» B. False

Discussion

16.	Full adders can add two numbers and need not have a carry input or a carry output.
A.	True
B.	False
Answer» C.

Discussion

17.	If no bits are designated inside square braces, [ ], it means the variable is the null set.
A.	True
B.	False
Answer» C.

Discussion

18.	The 74LS382 ALU is a 24-pin arithmetic/logic unit.
A.	True
B.	False
Answer» C.

Discussion

19.	The VHDL compiler requires libraries to be specified at the beginning of the code if components from those libraries are being used.
A.	True
B.	False
Answer» B. False

Discussion

20.	The carry-out of a binary adder is identified using the summation symbol, sigma.
A.	True
B.	False
Answer» C.

Discussion

21.	There are four possible combinations for subtracting two binary numbers.
A.	True
B.	False
Answer» B. False

Discussion

22.	The range of negative numbers when using an eight-bit two's-complement system is 1 to 128.
A.	True
B.	False
Answer» B. False

Discussion

23.	This logic gate is used to produce an arithmetic sum XOR.
A.	True
B.	False
Answer» B. False

Discussion

24.	A half-adder circuit would normally be used each time a carry input is required in an adder circuit.
A.	True
B.	False
Answer» C.

Discussion

25.	The binary subtraction 0 1 = isdifference = 1borrow = 0
A.	True
B.	False
Answer» C.

Discussion

26.	It is not necessary to have the same number of bits when adding or subtracting signed binary numbers in the 2's-complement system.
A.	True
B.	False
Answer» C.

Discussion

27.	Binary division and decimal division use the same procedure.
A.	True
B.	False
Answer» B. False

Discussion

28.	Full adder results are typically stored in registers.
A.	True
B.	False
Answer» B. False

Discussion

29.	The representation of 110 in eight-bit two's-complement notation is 11110111.
A.	True
B.	False
Answer» C.

Discussion

30.	111010002 is the 2's-complement representation of 24.
A.	True
B.	False
Answer» C.

Discussion

31.	When subtracting 6 from 9 using 2's-complement methods, the ________ is 2's complemented before the addition.
A.	six
B.	multiplier
C.	nine
D.	two
Answer» B. multiplier

Discussion

32.	When performing binary addition using the 2's-complement method, an ________ can occur if ________ are of the same ________; the error is indicated by a(n) ________.
A.	error, both numbers, magnitude, negative sign
B.	overflow, both numbers, sign, incorrect sign bit
C.	overflow, signs, magnitude, incorrect sum
D.	error, the signs, polarity, incorrect polarity
Answer» C. overflow, signs, magnitude, incorrect sum

Discussion

33.	Negation is performed by simply performing the ________ operation.
A.	1's-complement
B.	sign
C.	surrogate
D.	2's-complement
Answer» E.

Discussion

34.	The solution to the BCD problem 0101 + 0100 is 00001001BCD.
A.	True
B.	False
Answer» B. False

Discussion

35.	A macrofunction is a self-contained description of a logic circuit with all of its inputs, outputs, and operational characteristics defined.
A.	True
B.	False
Answer» B. False

Discussion

36.	A binary sum is made up of only 1s and 0s.
A.	True
B.	False
Answer» B. False

Discussion

37.	Overflow indicators in ALU circuits indicate when add or subtract operations produce results that are too large to fit into four bits.
A.	True
B.	False
Answer» B. False

Discussion

38.	The inputs of a full adder are labeled A1, B1, and Cin.
A.	True
B.	False
Answer» B. False

Discussion

39.	Larger number capacities may be obtained from 2-bit adders by paralleling them.
A.	True
B.	False
Answer» B. False

Discussion

40.	Binary numbers can be added together in a basic parallel-adder circuit when ________.
A.	negative numbers are in 2's-complement form
B.	negative numbers are in 1's-complement form
C.	all carry pins are grounded
D.	all negative numbers are noted
Answer» B. negative numbers are in 1's-complement form

Discussion

41.	To make an eight-bit adder from two four-bit adders you must connect ________.
A.	the high-order carry-in to ground
B.	the low-order carry-out to the high-order carry-in
C.	the high-order carry-out to ground
D.	the low-order sum to the high-order data input
Answer» C. the high-order carry-out to ground

Discussion

42.	Solve this binary problem: 01011000 00001011 = ________.
A.	1010
B.	0110
C.	1000
D.	1110
Answer» D. 1110

Discussion

43.	If [A] = 10 and [B] = 01, then [A] [b] = ________.
A.	[00]
B.	00
C.	11
D.	[11]
Answer» D. [11]

Discussion

44.	Packages are used to contain ________ and other information that must be available to all entities in the design file.
A.	types
B.	vectors
C.	components
D.	variables
Answer» D. variables

Discussion

45.	The inputs to an AND gate are: A = 1, B = 0, C = 1. The output will be LOW.
A.	True
B.	False
Answer» B. False

Discussion

46.	In Boolean algebra, 1 0 = 0.
A.	True
B.	False
Answer» B. False

Discussion

47.	The two's complement of 00001111 is ________.
A.	11111111
B.	11110000
C.	11110001
D.	11110111
Answer» D. 11110111

Discussion

48.	A 74HC283 can be used to implement a(n) ________ adder.
A.	4-bit BCD
B.	8-bit BCD
C.	4-bit full
D.	8-bit full
Answer» D. 8-bit full

Discussion

49.	Boolean multiplication is symbolized by A + B.
A.	True
B.	False
Answer» C.

Discussion

50.	910 represented in eight-bit two's-complement notation is ________.
A.	11110111
B.	11111001
C.	11110110
D.	01111101
Answer» B. 11111001

Discussion

Explore topic-wise MCQs in Testing Subject.

Fan-out for a typical TTL gate is ________.

The time it takes for an input signal to pass through internal circuitry and generate the appropriate output effect is known as ________.

A pull-down resistor must be used with open-collector TTL circuits.

The lower transistor of a totem-pole output is saturated when the gate output is ________.

Metal-oxide semiconductor field-effect transistors (MOSFETs) are the active switching elements in CMOS circuits.

Totem-pole outputs ________ be connected ________ because ________.

There are four different logic level ranges for TTL and CMOS: VIL, VIH, VOL, and VOH.

Power dissipation is a measure of a circuit's noise immunity.

The total sink current decreases with an increase in each load gate input.

The two's-complement method is used in computer systems that perform arithmetic.

Digital computers use an easier method to subtract binary numbers, called one's complement.

Binary multiplication is like decimal multiplication except you deal only with 1s and 0s.

The solution to the binary problem 1011 0111 is 1000.

A 74HC283 can be used to implement a 4-bit full adder.

When the 2's-complement system is used, the number to be subtracted is changed to its 2's complement and then added to the minuend.

Full adders can add two numbers and need not have a carry input or a carry output.

If no bits are designated inside square braces, [ ], it means the variable is the null set.

The 74LS382 ALU is a 24-pin arithmetic/logic unit.

The VHDL compiler requires libraries to be specified at the beginning of the code if components from those libraries are being used.

The carry-out of a binary adder is identified using the summation symbol, sigma.

There are four possible combinations for subtracting two binary numbers.

The range of negative numbers when using an eight-bit two's-complement system is 1 to 128.

This logic gate is used to produce an arithmetic sum XOR.

A half-adder circuit would normally be used each time a carry input is required in an adder circuit.

The binary subtraction 0 1 = isdifference = 1borrow = 0

It is not necessary to have the same number of bits when adding or subtracting signed binary numbers in the 2's-complement system.

Binary division and decimal division use the same procedure.

Full adder results are typically stored in registers.

The representation of 110 in eight-bit two's-complement notation is 11110111.

111010002 is the 2's-complement representation of 24.

When subtracting 6 from 9 using 2's-complement methods, the ________ is 2's complemented before the addition.

When performing binary addition using the 2's-complement method, an ________ can occur if ________ are of the same ________; the error is indicated by a(n) ________.

Negation is performed by simply performing the ________ operation.

The solution to the BCD problem 0101 + 0100 is 00001001BCD.

A macrofunction is a self-contained description of a logic circuit with all of its inputs, outputs, and operational characteristics defined.

A binary sum is made up of only 1s and 0s.

Overflow indicators in ALU circuits indicate when add or subtract operations produce results that are too large to fit into four bits.

The inputs of a full adder are labeled A1, B1, and Cin.

Larger number capacities may be obtained from 2-bit adders by paralleling them.

Binary numbers can be added together in a basic parallel-adder circuit when ________.

To make an eight-bit adder from two four-bit adders you must connect ________.

Solve this binary problem: 01011000 00001011 = ________.

If [A] = 10 and [B] = 01, then [A] [b] = ________.

Packages are used to contain ________ and other information that must be available to all entities in the design file.

The inputs to an AND gate are: A = 1, B = 0, C = 1. The output will be LOW.

In Boolean algebra, 1 0 = 0.

The two's complement of 00001111 is ________.

A 74HC283 can be used to implement a(n) ________ adder.

Boolean multiplication is symbolized by A + B.

910 represented in eight-bit two's-complement notation is ________.

Totem-pole outputs be connected because .

When performing binary addition using the 2's-complement method, an can occur if are of the same ; the error is indicated by a(n) .