2291 + Mcqs in Digital Electronics McqOptions

1.	Generally, PLDs can be described as being one of four different types.
A.	True
B.	False
Answer» C.

Discussion

2.	The programming technologies that are used in FPGA devices include SRAM, flash, and antifuse, with flash being most common.
A.	True
B.	False
Answer» C.

Discussion

3.	In ECL, the HIGH and LOW levels are determined by which transistor in a differential amplifier is conducting more.
A.	True
B.	False
Answer» B. False

Discussion

4.	Propagation delay in TTL is due to slow switching speeds.
A.	True
B.	False
Answer» C.

Discussion

5.	In TTL the noise margin is between 0.8 V and 0.4 V.
A.	True
B.	False
Answer» B. False

Discussion

6.	The AND is the simplest of the gates, requiring the least amount of circuitry to implement in TTL.
A.	True
B.	False
Answer» C.

Discussion

7.	A decimal fraction can be converted to binary by using the repeated division-by-2 method.
A.	True
B.	False
Answer» C.

Discussion

8.	The PAL has an AND and OR structure similar to a PROM, but in the PAL the inputs to the AND gates are programmable, whereas the inputs to the OR gate are hard-wired.
A.	True
B.	False
Answer» B. False

Discussion

9.	Gate arrays are ULSI circuits that offer hundreds of thousands of gates.
A.	True
B.	False
Answer» B. False

Discussion

10.	Schematic capture is a process performed by PLD software.
A.	True
B.	False
Answer» B. False

Discussion

11.	An expensive form of programmable logic is SPLD.
A.	True
B.	False
Answer» C.

Discussion

12.	The FPLA has a programmable AND array and a programmable OR array.
A.	True
B.	False
Answer» B. False

Discussion

13.	Using a hardware solution for your digital system design is always faster than a software solution.
A.	True
B.	False
Answer» B. False

Discussion

14.	Altera Corporation and Xilinx Corporation are the two leading PLD manufacturers.
A.	True
B.	False
Answer» B. False

Discussion

15.	The hard core portions of FPGAs are reprogrammable in the field.
A.	True
B.	False
Answer» C.

Discussion

16.	A GAL22V10 ________.
A.	has up to 32 inputs and 10 outputs
B.	is a type of SPLD
C.	has 10 inputs and 22 outputs
D.	is downloadable from the manufacturer's Web site
Answer» C. has 10 inputs and 22 outputs

Discussion

17.	Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions.
A.	AND array
B.	Look-up table
C.	OR array
D.	AND and OR array
Answer» C. OR array

Discussion

18.	The Boolean expression AB + CD is an example of ________.
A.	PAL
B.	GAL
C.	SOP
D.	POS
Answer» D. POS

Discussion

19.	In a programmable logic device circuit diagram, the inputs to each of the OR gates are designated by ________.
A.	a dot
B.	a bus
C.	a single line
D.	4 inputs
Answer» D. 4 inputs

Discussion

20.	The SPLD classification includes the ________ PLD devices.
A.	earliest
B.	smallest
C.	largest
D.	newest
Answer» B. smallest

Discussion

21.	The ________ can generate any possible logic function of the input variables because it generates every possible AND product term.
A.	GAL
B.	SOP
C.	PROM
D.	LAB
Answer» D. LAB

Discussion

22.	The EPM 7128S is a(n) ________ device.
A.	PLD
B.	JTAG
C.	EEPROM
D.	ISP
Answer» E.

Discussion

23.	________ is a mature technology consisting of numerous subfamilies that have been developed over many years of use.
A.	TTL
B.	CMOS
C.	ECL
D.	None of the above
Answer» B. CMOS

Discussion

24.	Full custom ICs can operate at ________ and require the ________.
A.	lowest speed, largest die area
B.	lowest speed, smallest die area
C.	highest speed, largest die area
D.	highest speed, smallest die area
Answer» E.

Discussion

25.	A macrocell is ________.
A.	part of a PAL or GAL
B.	a type of one-time programmable SPLD
C.	an example of intellectual property
D.	a logic array block
Answer» B. a type of one-time programmable SPLD

Discussion

26.	Using a hardware solution for a digital system is always ________ than a software solution.
A.	slower
B.	harder
C.	easier
D.	faster
Answer» E.

Discussion

27.	The programming technologies that are used in FPGA devices include SRAM, flash, and antifuse, with ________ being the most common.
A.	SRAM
B.	flash
C.	antifuse
D.	SRAM and flash
Answer» B. flash

Discussion

28.	The final step in a design flow in which the logic design is implemented in the target device is called ________.
A.	design entry
B.	simulation
C.	downloading
D.	compiling
Answer» D. compiling

Discussion

29.	A method for the automated testing of printed circuit boards is called a(n) ________.
A.	bed-of-nails
B.	LUT
C.	CLB
D.	CPLD
Answer» B. LUT

Discussion

30.	In a MAX7000S device, when an I/O pin is configured as an input, the associated macrocell can be used for ________.
A.	buried logic
B.	another output
C.	extra speed
D.	in-system testing
Answer» B. another output

Discussion

31.	The process or sequence of all operations carried out to ultimately program a target device is called the ________.
A.	graphic entry
B.	LAB
C.	downloading
D.	design flow
Answer» E.

Discussion

32.	In the GAL16V8, the ________ controls the tristate buffer's enable input.
A.	FMUX
B.	OMUX
C.	PTMUX
D.	TMUX
Answer» E.

Discussion

33.	All inputs to the MAX7000S device and all macrocell outputs feed the ________.
A.	LUT
B.	PIA
C.	LAB
D.	PIA and LAB
Answer» C. LAB

Discussion

34.	A ring counter is a register in which a certain pattern of 1s and 0s is continuously outputted in parallel.
A.	True
B.	False
Answer» B. False

Discussion

35.	In the GAL16V8, the ________ selects the signal that is fed back into the input matrix.
A.	FMUX
B.	OMUX
C.	PTMUX
D.	TSMUX
Answer» B. OMUX

Discussion

36.	An application program in the development software package that controls the operation of the software is called a ________.
A.	compiler
B.	bed-of-nails
C.	boundary scan
D.	primitive
Answer» B. bed-of-nails

Discussion

37.	Bidirectional means having two states.
A.	True
B.	False
Answer» C.

Discussion

38.	Eight states are in an 8-bit Johnson counter sequence.
A.	True
B.	False
Answer» C.

Discussion

39.	A stage is two storage elements in a register.
A.	True
B.	False
Answer» C.

Discussion

40.	When is LOW, the data are shifted one bit per clock pulse.
A.	True
B.	False
Answer» C.

Discussion

41.	The flexibility of the GAL16V8 is in its ________.
A.	AND/OR array
B.	D flip-flops
C.	programmable output logic macro cells
D.	EEPROM
Answer» D. EEPROM

Discussion

42.	Design costs for standard cell ASICs are ________ those for MPGAs.
A.	lower than
B.	about the same as
C.	higher than
D.	none of the above
Answer» D. none of the above

Discussion

43.	A stepper motor makes its rotation in smooth continuous motion.
A.	True
B.	False
Answer» C.

Discussion

44.	A universal shift register has both serial and parallel input and output capacity.
A.	True
B.	False
Answer» B. False

Discussion

45.	The storage capacity of a register makes it an important type of memory.
A.	True
B.	False
Answer» B. False

Discussion

46.	The 74194 4-bit bidirectional universal shift register has a wide range of applications.
A.	True
B.	False
Answer» B. False

Discussion

47.	In a 74164 8-bit shift register, in order for the parallel data output to be synchronously loaded on the negative clock edge, the parallel enable input is LOW.
A.	True
B.	False
Answer» C.

Discussion

48.	Practically every possible load, shift, and conversion operation is available in a shift register IC.
A.	True
B.	False
Answer» B. False

Discussion

49.	Adding an odd-parity bit to ASCII hex code 2B results in 10101011.
A.	True
B.	False
Answer» B. False

Discussion

50.	The hexadecimal numbering system uses base 15.
A.	True
B.	False
Answer» C.

Discussion

Explore topic-wise MCQs in Testing Subject.

Generally, PLDs can be described as being one of four different types.

The programming technologies that are used in FPGA devices include SRAM, flash, and antifuse, with flash being most common.

In ECL, the HIGH and LOW levels are determined by which transistor in a differential amplifier is conducting more.

Propagation delay in TTL is due to slow switching speeds.

In TTL the noise margin is between 0.8 V and 0.4 V.

The AND is the simplest of the gates, requiring the least amount of circuitry to implement in TTL.

A decimal fraction can be converted to binary by using the repeated division-by-2 method.

The PAL has an AND and OR structure similar to a PROM, but in the PAL the inputs to the AND gates are programmable, whereas the inputs to the OR gate are hard-wired.

Gate arrays are ULSI circuits that offer hundreds of thousands of gates.

Schematic capture is a process performed by PLD software.

An expensive form of programmable logic is SPLD.

The FPLA has a programmable AND array and a programmable OR array.

Using a hardware solution for your digital system design is always faster than a software solution.

Altera Corporation and Xilinx Corporation are the two leading PLD manufacturers.

The hard core portions of FPGAs are reprogrammable in the field.

A GAL22V10 ________.

Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions.

The Boolean expression AB + CD is an example of ________.

In a programmable logic device circuit diagram, the inputs to each of the OR gates are designated by ________.

The SPLD classification includes the ________ PLD devices.

The ________ can generate any possible logic function of the input variables because it generates every possible AND product term.

The EPM 7128S is a(n) ________ device.

________ is a mature technology consisting of numerous subfamilies that have been developed over many years of use.

Full custom ICs can operate at ________ and require the ________.

A macrocell is ________.

Using a hardware solution for a digital system is always ________ than a software solution.

The programming technologies that are used in FPGA devices include SRAM, flash, and antifuse, with ________ being the most common.

The final step in a design flow in which the logic design is implemented in the target device is called ________.

A method for the automated testing of printed circuit boards is called a(n) ________.

In a MAX7000S device, when an I/O pin is configured as an input, the associated macrocell can be used for ________.

The process or sequence of all operations carried out to ultimately program a target device is called the ________.

In the GAL16V8, the ________ controls the tristate buffer's enable input.

All inputs to the MAX7000S device and all macrocell outputs feed the ________.

A ring counter is a register in which a certain pattern of 1s and 0s is continuously outputted in parallel.

In the GAL16V8, the ________ selects the signal that is fed back into the input matrix.

An application program in the development software package that controls the operation of the software is called a ________.

Bidirectional means having two states.

Eight states are in an 8-bit Johnson counter sequence.

A stage is two storage elements in a register.

When is LOW, the data are shifted one bit per clock pulse.

The flexibility of the GAL16V8 is in its ________.

Design costs for standard cell ASICs are ________ those for MPGAs.

A stepper motor makes its rotation in smooth continuous motion.

A universal shift register has both serial and parallel input and output capacity.

The storage capacity of a register makes it an important type of memory.

The 74194 4-bit bidirectional universal shift register has a wide range of applications.

In a 74164 8-bit shift register, in order for the parallel data output to be synchronously loaded on the negative clock edge, the parallel enable input is LOW.

Practically every possible load, shift, and conversion operation is available in a shift register IC.

Adding an odd-parity bit to ASCII hex code 2B results in 10101011.

The hexadecimal numbering system uses base 15.

Full custom ICs can operate at and require the .