2291 + Mcqs in Digital Electronics McqOptions

1.	The field programmable logic array was the first ________ programmable logic device.
A.	understandable
B.	logic array
C.	multifunction
D.	nonmemory
Answer» E.

Discussion

2.	In a GAL16V8, the D flip-flops contained in the OLMCs have ________ and ________.
A.	asynchronous reset, synchronous preset
B.	asynchronous preset, synchronous reset
C.	asynchronous clear, synchronous set
D.	asynchronous set, synchronous clear
Answer» B. asynchronous preset, synchronous reset

Discussion

3.	SPLD is a program language used by PLD software.
A.	True
B.	False
Answer» C.

Discussion

4.	CPLDs and FPGAs are often referred to as high-capacity programmable logic devices (HCPLDs).
A.	True
B.	False
Answer» B. False

Discussion

5.	In a PLD, a blown fuse at an OR gate is a LOW and a blown fuse at an AND gate is a HIGH.
A.	True
B.	False
Answer» B. False

Discussion

6.	1510 = 11112 = F16 = 00010101 BCD
A.	True
B.	False
Answer» B. False

Discussion

7.	A type of shift register that requires access to the Q outputs of all stages is ________.
A.	parallel in/serial out
B.	serial in/parallel out
C.	serial in/serial out
D.	a bidirectional shift register
Answer» C. serial in/serial out

Discussion

8.	The Altera UPIX educational development board contains an EP10K60 device in a 280-pin package.
A.	True
B.	False
Answer» C.

Discussion

9.	When the analog input to a tracking A/D converter is at a constant level, the digital output will oscillate.
A.	True
B.	False
Answer» B. False

Discussion

10.	To be useful, A/D or D/A converters must have meaningful representation of the analog quantity and a digital representation and the digital quantity as an analog representation.
A.	True
B.	False
Answer» B. False

Discussion

11.	A sample-and-hold circuit is used in D/A conversion.
A.	True
B.	False
Answer» C.

Discussion

12.	The output of an analog-to-digital converter is a voltage level.
A.	True
B.	False
Answer» C.

Discussion

13.	The digit bus and display bus are each just a common set of conductors shared by the digit storage registers and display segments.
A.	True
B.	False
Answer» B. False

Discussion

14.	A light bulb and a switch are examples of an analog circuit.
A.	True
B.	False
Answer» C.

Discussion

15.	When a DAC output shows a deviation of the measured step size from the ideal step size, this error is called nonlinearity.
A.	True
B.	False
Answer» B. False

Discussion

16.	In a digital storage scope, when memory is full, the next data point is lost.
A.	True
B.	False
Answer» C.

Discussion

17.	The basic comparator evaluates two binary strings bit by bit and always outputs a 1.
A.	True
B.	False
Answer» C.

Discussion

18.	The term synchronous, as applied to counter operations, means that the counter is clocked such that each flip-flop in the counter is triggered at the same time.
A.	True
B.	False
Answer» B. False

Discussion

19.	A 2-input gate that can be used to pass a digital waveform unchanged at certain times and inverted at other times is a(n) ________.
A.	AND gate
B.	OR gate
C.	NAND gate
D.	XOR gate
Answer» E.

Discussion

20.	The gates in this figure are implemented using TTL logic. If the output of the inverter has an internal open circuit, what voltage would you expect to measure at the inverter's output?
A.	Less than 0.4 V
B.	1.6 V
C.	Greater than 2.4 V
D.	All of the above
Answer» C. Greater than 2.4 V

Discussion

21.	A pulse is not perfectly square; it takes time for the digital level to rise from 0 up to 1 and to fall from 1 down to 0.
A.	True
B.	False
Answer» B. False

Discussion

22.	PMOS and NMOS are commonly used for small memories and microprocessors.
A.	True
B.	False
Answer» C.

Discussion

23.	Based on the high-density architecture of logic cells, FLEX10K devices are generally classified as HCPLDs.
A.	True
B.	False
Answer» C.

Discussion

24.	A CPLD is basically a simplified PLD.
A.	True
B.	False
Answer» C.

Discussion

25.	The GAL16V8 has 32 input variables.
A.	True
B.	False
Answer» B. False

Discussion

26.	Xilinx software uses triangular symbols called buffers to define pins as input or output.
A.	True
B.	False
Answer» C.

Discussion

27.	LUT is an acronym for look-up table.
A.	True
B.	False
Answer» B. False

Discussion

28.	A PAL uses a programmable OR array followed by a fixed AND array.
A.	True
B.	False
Answer» C.

Discussion

29.	The SRAM technology is volatile.
A.	True
B.	False
Answer» B. False

Discussion

30.	The architecture of a PAL differs slightly from that of a PROM.
A.	True
B.	False
Answer» B. False

Discussion

31.	The MAX+PLUS II compiler will automatically program a macrocell to borrow up to six product terms from each of three adjacent macrocells in the same LAB.
A.	True
B.	False
Answer» C.

Discussion

32.	The major structures of the MAX7000S are the logic array block (LAB) and the programmable intermediate array (PIA).
A.	True
B.	False
Answer» C.

Discussion

33.	All I/O pins in the MAX7000S family have a tristate buffer.
A.	True
B.	False
Answer» B. False

Discussion

34.	Antifuse devices are volatile.
A.	True
B.	False
Answer» C.

Discussion

35.	The GAL16V8 has eight dedicated input pins.
A.	True
B.	False
Answer» B. False

Discussion

36.	In the FLEX10K device, the LE can produce two outputs to drive local (LAB) and global (fast track) interconnects on the chip.
A.	True
B.	False
Answer» B. False

Discussion

37.	The major digital system categories include Boolean logic, ASICs, and microprocessor/DSP devices.
A.	True
B.	False
Answer» C.

Discussion

38.	With microcomputer/DSP systems, devices can be electronically controlled and data can be manipulated by executing a program of instructions that has been written for the application.
A.	True
B.	False
Answer» B. False

Discussion

39.	The GAL chip uses an EEPROM array that is erasable and reprogrammable at least 1000 times.
A.	True
B.	False
Answer» C.

Discussion

40.	The Altera FLEX10K family uses a look-up table (LUT) architecture.
A.	True
B.	False
Answer» B. False

Discussion

41.	PLDs cannot meet all the possible requirements of complex digital circuitry.
A.	True
B.	False
Answer» C.

Discussion

42.	The four input-only pins found on devices in the MAX7000S family can be configured as specific high-speed control signals or as general user inputs.
A.	True
B.	False
Answer» B. False

Discussion

43.	In the OLMC of a GAL16V8, the FMUX selects the signal that is fed into the input matrix.
A.	True
B.	False
Answer» B. False

Discussion

44.	A PAL consists of an array of fixed AND gates that are connected to a programmable array of OR gates.
A.	True
B.	False
Answer» C.

Discussion

45.	VHDL code is divided into three sections: library declaration, entity declaration, and architecture body.
A.	True
B.	False
Answer» B. False

Discussion

46.	The schematic editor allows you to connect with predefined logic symbols.
A.	True
B.	False
Answer» B. False

Discussion

47.	All inputs to the MAX7000S device and all macrocell outputs feed the PIA.
A.	True
B.	False
Answer» B. False

Discussion

48.	Sum-of-products is two or more product terms that are NANDed together.
A.	True
B.	False
Answer» C.

Discussion

49.	Most complex digital designs include a mix of different hardware categories.
A.	True
B.	False
Answer» B. False

Discussion

50.	The number of input combinations for a 4-input gate is ________.
A.	9
B.	8
C.	15
D.	16
Answer» E.

Discussion

Explore topic-wise MCQs in Testing Subject.

The field programmable logic array was the first ________ programmable logic device.

In a GAL16V8, the D flip-flops contained in the OLMCs have ________ and ________.

SPLD is a program language used by PLD software.

CPLDs and FPGAs are often referred to as high-capacity programmable logic devices (HCPLDs).

In a PLD, a blown fuse at an OR gate is a LOW and a blown fuse at an AND gate is a HIGH.

1510 = 11112 = F16 = 00010101 BCD

A type of shift register that requires access to the Q outputs of all stages is ________.

The Altera UPIX educational development board contains an EP10K60 device in a 280-pin package.

When the analog input to a tracking A/D converter is at a constant level, the digital output will oscillate.

To be useful, A/D or D/A converters must have meaningful representation of the analog quantity and a digital representation and the digital quantity as an analog representation.

A sample-and-hold circuit is used in D/A conversion.

The output of an analog-to-digital converter is a voltage level.

The digit bus and display bus are each just a common set of conductors shared by the digit storage registers and display segments.

A light bulb and a switch are examples of an analog circuit.

When a DAC output shows a deviation of the measured step size from the ideal step size, this error is called nonlinearity.

In a digital storage scope, when memory is full, the next data point is lost.

The basic comparator evaluates two binary strings bit by bit and always outputs a 1.

The term synchronous, as applied to counter operations, means that the counter is clocked such that each flip-flop in the counter is triggered at the same time.

A 2-input gate that can be used to pass a digital waveform unchanged at certain times and inverted at other times is a(n) ________.

The gates in this figure are implemented using TTL logic. If the output of the inverter has an internal open circuit, what voltage would you expect to measure at the inverter's output?

A pulse is not perfectly square; it takes time for the digital level to rise from 0 up to 1 and to fall from 1 down to 0.

PMOS and NMOS are commonly used for small memories and microprocessors.

Based on the high-density architecture of logic cells, FLEX10K devices are generally classified as HCPLDs.

A CPLD is basically a simplified PLD.

The GAL16V8 has 32 input variables.

Xilinx software uses triangular symbols called buffers to define pins as input or output.

LUT is an acronym for look-up table.

A PAL uses a programmable OR array followed by a fixed AND array.

The SRAM technology is volatile.

The architecture of a PAL differs slightly from that of a PROM.

The MAX+PLUS II compiler will automatically program a macrocell to borrow up to six product terms from each of three adjacent macrocells in the same LAB.

The major structures of the MAX7000S are the logic array block (LAB) and the programmable intermediate array (PIA).

All I/O pins in the MAX7000S family have a tristate buffer.

Antifuse devices are volatile.

The GAL16V8 has eight dedicated input pins.

In the FLEX10K device, the LE can produce two outputs to drive local (LAB) and global (fast track) interconnects on the chip.

The major digital system categories include Boolean logic, ASICs, and microprocessor/DSP devices.

With microcomputer/DSP systems, devices can be electronically controlled and data can be manipulated by executing a program of instructions that has been written for the application.

The GAL chip uses an EEPROM array that is erasable and reprogrammable at least 1000 times.

The Altera FLEX10K family uses a look-up table (LUT) architecture.

PLDs cannot meet all the possible requirements of complex digital circuitry.

The four input-only pins found on devices in the MAX7000S family can be configured as specific high-speed control signals or as general user inputs.

In the OLMC of a GAL16V8, the FMUX selects the signal that is fed into the input matrix.

A PAL consists of an array of fixed AND gates that are connected to a programmable array of OR gates.

VHDL code is divided into three sections: library declaration, entity declaration, and architecture body.

The schematic editor allows you to connect with predefined logic symbols.

All inputs to the MAX7000S device and all macrocell outputs feed the PIA.

Sum-of-products is two or more product terms that are NANDed together.

Most complex digital designs include a mix of different hardware categories.

The number of input combinations for a 4-input gate is ________.

In a GAL16V8, the D flip-flops contained in the OLMCs have and .