MCQOPTIONS
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MCQOPTIONS
This section includes 657 Mcqs, each offering curated multiple-choice questions to sharpen your Testing Subject knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
directive specifies the end of execution of a program. |
| A. | end |
| B. | return |
| C. | stop |
| D. | terminate |
| Answer» C. stop | |
| 2. |
is an extension of the processor BUS. |
| A. | scsi bus |
| B. | usb |
| C. | pci bus |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 3. |
A gate is used to detect the occurrence of an overflow. |
| A. | nand |
| B. | xor |
| C. | xnor |
| D. | and |
| Answer» C. xnor | |
| 4. |
In register transfer the processor register as: |
| A. | MAR |
| B. | PC |
| C. | IR |
| D. | RI |
| Answer» E. | |
| 5. |
Which of the following register is used in the control unit of the CPU to indicate the next instruction which is to be executed ? |
| A. | Accumulator |
| B. | Index register |
| C. | Instruction decoder |
| D. | Program counter |
| Answer» E. | |
| 6. |
The effective address of the following instruction is MUL 5(R1,R2). |
| A. | 5+R1+R2 |
| B. | 5+(R1*R2) |
| C. | 5+[R1]+[R2] |
| D. | 5*([R1]+[R2]) |
| Answer» D. 5*([R1]+[R2]) | |
| 7. |
Which language is termed as the symbolic depiction used for indicating the series: |
| A. | Random transfer language |
| B. | Register transfer language |
| C. | Arithmetic transfer language |
| D. | All of these |
| Answer» C. Arithmetic transfer language | |
| 8. |
If a processor does not have any stack pointer register, then |
| A. | It cannot have subroutine call instruction |
| B. | It can have subroutine call instruction, but no nested subroutine |
| C. | Nested subroutine calls are possible, but interrupts are not |
| D. | All sequences of subroutine calls and also interrupts are |
| Answer» E. | |
| 9. |
In IBM’s S360/370 systems lines are used toselect the I/O devices. |
| A. | SCAN in and out |
| B. | Connect |
| C. | Search |
| D. | Peripheral |
| Answer» B. Connect | |
| 10. |
The method of writing symbol to indicate a provided computational process is called as a: |
| A. | Programming language |
| B. | Random transfer language |
| C. | Register transfer language |
| D. | Arithmetic transfer language |
| Answer» B. Random transfer language | |
| 11. |
The less space consideration as lead to the development of (for large memories). |
| A. | SIMM’s |
| B. | DIMS’s |
| C. | SRAM’s |
| D. | Both SIMM’s and DIMS’s |
| Answer» E. | |
| 12. |
Which are the operation that a computer performs on data that put in register: |
| A. | Register transfer |
| B. | Arithmetic |
| C. | Logical |
| D. | All of these |
| Answer» E. | |
| 13. |
Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read operation. Then the refresh overhead of the chip is |
| A. | 0.0021 |
| B. | 0.0038 |
| C. | 0.0064 |
| D. | 0.0128 |
| Answer» C. 0.0064 | |
| 14. |
In memory read the operation puts memory address on to a register known as : |
| A. | PC |
| B. | ALU |
| C. | MR |
| D. | All of these |
| Answer» D. All of these | |
| 15. |
RTL stands for: |
| A. | Random transfer language |
| B. | Register transfer language |
| C. | Arithmetic transfer language |
| D. | All of these |
| Answer» C. Arithmetic transfer language | |
| 16. |
The Sun micro systems processors usually follow architecture. |
| A. | CISC |
| B. | ISA |
| C. | ULTRA SPARC |
| D. | RISC |
| Answer» E. | |
| 17. |
Which operation puts memory address in memory address register and data in DR: |
| A. | Memory read |
| B. | Memory Write |
| C. | Both |
| D. | None |
| Answer» C. Both | |
| 18. |
addressing mode is most suitable to change the normal sequence of execution of instructions. |
| A. | Relative |
| B. | Indirect |
| C. | Index with Offset |
| D. | Immediate |
| Answer» B. Indirect | |
| 19. |
How many types of micro operations: |
| A. | 2 |
| B. | 4 |
| C. | 6 |
| D. | 8 |
| Answer» C. 6 | |
| 20. |
The register that includes the address of the memory unit is termed as the : |
| A. | MAR |
| B. | PC |
| C. | IR |
| D. | None of these |
| Answer» B. PC | |
| 21. |
The master indicates that the address is loaded onto the BUS, by activating signal. |
| A. | MSYN |
| B. | SSYN |
| C. | WMFC |
| D. | INTR |
| Answer» B. SSYN | |
| 22. |
Which operations are used for addition, subtraction, increment, decrement and complement function: |
| A. | Bus |
| B. | Memory transfer |
| C. | Arithmetic operation |
| D. | All of these |
| Answer» E. | |
| 23. |
Computer address bus is |
| A. | bidirectional |
| B. | unidirectional |
| C. | multidirectional |
| D. | circular |
| Answer» C. multidirectional | |
| 24. |
In 32-bit addressing mode, the address field is either 1 byte or |
| A. | 2 bytes |
| B. | 3 bytes |
| C. | 4 bytes |
| D. | 5 bytes |
| Answer» D. 5 bytes | |
| 25. |
Optimizations on the sources with output leading to later optimization passes are known as |
| A. | Low-level optimizations |
| B. | High-level optimizations |
| C. | Local optimizations |
| D. | Global optimizations |
| Answer» C. Local optimizations | |
| 26. |
To increase the performance of the computer its through put is increased by |
| A. | Replacing processor with faster version |
| B. | Replacing input/output |
| C. | Replacing Operating System |
| D. | Replacing Cache |
| Answer» B. Replacing input/output | |
| 27. |
Computer bus with 64 lines can carry |
| A. | 32bits |
| B. | 64bits |
| C. | 16bits |
| D. | 8bits |
| Answer» C. 16bits | |
| 28. |
Compiler of the system, is an example of |
| A. | System hardware |
| B. | Input |
| C. | System software |
| D. | Output |
| Answer» D. Output | |
| 29. |
Replacing the instances of a variable, to which a constant is assigned with the constant, is refered as |
| A. | Global common sub-expression elimination |
| B. | Stack height reduction |
| C. | Heap |
| D. | Constant propagation |
| Answer» E. | |
| 30. |
The operation is normally specified in one field, known as |
| A. | Oprand |
| B. | Opcode |
| C. | Operation |
| D. | Instruction count |
| Answer» C. Operation | |
| 31. |
Use of computer buses to connect different components of computer is known as |
| A. | bus interconnection |
| B. | layout of computer components |
| C. | computer structure |
| D. | bus topology |
| Answer» B. layout of computer components | |
| 32. |
The information's components in base 2 are |
| A. | 0 |
| B. | 1 |
| C. | integers |
| D. | both a and b |
| Answer» E. | |
| 33. |
A set of standard CPU-intensive, floating points and integers benchmarks are referred to as |
| A. | SPEC benchmark |
| B. | PEC benchmark |
| C. | SEC benchmark |
| D. | SQEC benchmark |
| Answer» B. PEC benchmark | |
| 34. |
Example of computer logic operation is |
| A. | AND |
| B. | OR |
| C. | NOR |
| D. | all of these |
| Answer» E. | |
| 35. |
Computer system mainly consists of |
| A. | CPU |
| B. | main memory |
| C. | I/O unit |
| D. | all of these |
| Answer» E. | |
| 36. |
Network topology in which you connect each node to the network along a single piece of network cable is called |
| A. | bus topology |
| B. | ring topology |
| C. | star topology |
| D. | mesh topology |
| Answer» B. ring topology | |
| 37. |
The optimization: finding two examples of an expression, computing the same value and saving the value of the 1st computation in a temporary variable, is refered as |
| A. | Global common sub-expression elimination |
| B. | Global sub-expression elimination |
| C. | Global elimination |
| D. | Sub-expression elimination |
| Answer» B. Global sub-expression elimination | |
| 38. |
Which of the following is not a type of bus in computer? |
| A. | data bus |
| B. | address bus |
| C. | timer bus |
| D. | control bus |
| Answer» D. control bus | |
| 39. |
Most of time, computer instructions are divided into |
| A. | function code |
| B. | instruction code |
| C. | operand |
| D. | both a and c |
| Answer» E. | |
| 40. |
The total amount of work done during execution, in a given time is referred to as |
| A. | Response time |
| B. | Execution time |
| C. | Through put |
| D. | Delay time |
| Answer» D. Delay time | |
| 41. |
The processor having Clock cycle of 0.25ns will have the clock rate of |
| A. | 2GHz |
| B. | 3GHz |
| C. | 4GHz |
| D. | 8GHz |
| Answer» D. 8GHz | |
| 42. |
The valid and unimpeachable measurement of performance of any computer is |
| A. | Clock rate |
| B. | Instruction set |
| C. | Execution time |
| D. | Delay time |
| Answer» D. Delay time | |
| 43. |
CPU provides enabling signals through |
| A. | control bus |
| B. | data bus |
| C. | address bus |
| D. | ordinary bus |
| Answer» B. data bus | |
| 44. |
Built-in set of machine code instructions of computer are called |
| A. | instruction set |
| B. | transfer of data |
| C. | logical operations |
| D. | logical set |
| Answer» B. transfer of data | |
| 45. |
In a computer, set of electrical paths which is used to transfer data is called |
| A. | bus |
| B. | monitors |
| C. | computer clock |
| D. | ports |
| Answer» B. monitors | |
| 46. |
Special resistor device in computer bus network topology which is attached to an electrical ground is called |
| A. | terminator |
| B. | transistor |
| C. | switch |
| D. | sensor |
| Answer» B. transistor | |
| 47. |
Specified telling that what addressing mode will be used for accessing the operand, is called |
| A. | Address specified |
| B. | Binary-coded decimal |
| C. | Unpacking |
| D. | Packed decimal |
| Answer» B. Binary-coded decimal | |
| 48. |
Unit is used for allocating dynamic objects which do not adhere to the stack discipline is |
| A. | Queue |
| B. | Stack |
| C. | Heap |
| D. | Banks |
| Answer» D. Banks | |
| 49. |
One that is used to allocate local variables is |
| A. | Queue |
| B. | Stack |
| C. | Registers |
| D. | Banks |
| Answer» C. Registers | |
| 50. |
In assembly language A-B will be written as |
| A. | sub AB |
| B. | subtraction AB |
| C. | sub A,B |
| D. | subtraction A,B |
| Answer» D. subtraction A,B | |