950 + Mcqs in Computer Architecture McqOptions

1.	The 68000 uses Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â method to access I/O devices buffers.
A.	memory mapped
B.	i/o mapped
C.	buffer mapped
D.	none of the mentioned
Answer» B. i/o mapped

Discussion

2.	The instructions in 68000 can deal with operands of three different sizes.
A.	true
B.	false
Answer» B. false

Discussion

3.	Instructions which can handle any type of addressing mode are said to be
A.	omniscient
B.	orthogonal
C.	versatile
D.	none of the mentioned
Answer» C. versatile

Discussion

4.	The addresses generated by the 68000 is Â Â Â Â Â Â Â Â Â Â Â bit.
A.	32
B.	16
C.	24
D.	42
Answer» D. 42

Discussion

5.	The 68000 uses Â Â Â Â Â Â Â Â Â Â Â address assignment.
A.	big endian
B.	little endian
C.	x-little endian
D.	x-big endian
Answer» B. little endian

Discussion

6.	When an operand is stored in a register it is
A.	stored in the lower order bits of the register
B.	stored in the higher order bits of the register
C.	stored in any of the bits at random
D.	none of the mentioned
Answer» B. stored in the higher order bits of the register

Discussion

7.	The 68000 has a max of how many data registers?
A.	16
B.	20
C.	10
D.	8
Answer» E.

Discussion

8.	Is 68000 computer Byte addressable?
A.	true
B.	false
Answer» B. false

Discussion

9.	The register in 68000 can contain up to Â Â Â Â Â Â Â Â Â Â Â bits.
A.	24
B.	32
C.	16
D.	64
Answer» C. 16

Discussion

10.	The general purpose registers are combined into a block called as
A.	register bank
B.	register case
C.	register file
D.	none of the mentioned
Answer» D. none of the mentioned

Discussion

11.	Whenever a request to the page that is not present in the main memory is accessed Â Â Â Â Â Â Â Â Â Â Â Â Â Â is triggered.
A.	interrupt
B.	request
C.	page fault
D.	none of the mentioned
Answer» D. none of the mentioned

Discussion

12.	The word length in the 68000 computer is
A.	32 bit
B.	64 bit
C.	16 bit
D.	8 bit
Answer» D. 8 bit

Discussion

13.	Â Â Â Â Â Â Â Â Â Â Â register is designated to point to the 68000 processor stack.
A.	a7 register
B.	b2 register
C.	there is no such designation
D.	any general purpose register is selected at random
Answer» B. b2 register

Discussion

14.	What does the RUN signal do?
A.	it causes the termination of a signal
B.	it causes a particular signal to perform its operation
C.	it causes a particular signal to end
D.	it increments the step counter by one
Answer» E.

Discussion

15.	The TLB is incorporated as part of the
A.	processor
B.	mmu
C.	disk
D.	ram
Answer» C. disk

Discussion

16.	When the page table is placed in the main memory, the Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â is used to store the recently accessed pages.
A.	mmu
B.	tlb
C.	r0
D.	table
Answer» C. r0

Discussion

17.	If the page table is large then it is stored in
A.	processor
B.	main memory
C.	disk
D.	secondary storage
Answer» C. disk

Discussion

18.	The page table should be ideally situated within
A.	processor
B.	tlb
C.	mmu
D.	cache
Answer» D. cache

Discussion

19.	The bit used to store whether the page has been modified or not is called as
A.	dirty bit
B.	modify bit
C.	relocation bit
D.	none of the mentioned
Answer» B. modify bit

Discussion

20.	The bits used to indicate the status of the page in the memory is called
A.	control bits
B.	status bits
C.	progress bit
D.	none of the mentioned
Answer» B. status bits

Discussion

21.	The Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â bit is used to indicate the validity of the page.
A.	valid bit
B.	invalid bit
C.	correct bit
D.	none of the mentioned
Answer» B. invalid bit

Discussion

22.	The starting address of the page table is stored in
A.	tlb
B.	r0
C.	page table base register
D.	none of the mentioned
Answer» D. none of the mentioned

Discussion

23.	The area in the main memory that can hold one page is called as
A.	page entry
B.	page frame
C.	frame
D.	block
Answer» C. frame

Discussion

24.	The lower order bits of the virtual address forms the
A.	page number
B.	frame number
C.	block number
D.	offset
Answer» E.

Discussion

25.	The higher order bits of the virtual address generated by the processor forms the
A.	table number
B.	frame number
C.	list number
D.	page number
Answer» E.

Discussion

26.	The cache bridges the speed gap between Â Â Â Â Â Â Â Â Â Â Â Â Â Â and
A.	ram and rom
B.	ram and secondary memory
C.	processor and ram
D.	none of the mentioned
Answer» D. none of the mentioned

Discussion

27.	The pages size shouldnâ€™t be too small, as this would lead to
A.	transfer errors
B.	increase in operation time
C.	increase in access time
D.	decrease in performance
Answer» D. decrease in performance

Discussion

28.	The page length shouldnâ€™t be too long because
A.	it reduces the program efficiency
B.	it increases the access time
C.	it leads to wastage of memory
D.	none of the mentioned
Answer» D. none of the mentioned

Discussion

29.	The virtual memory bridges the size and speed gap between Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â and
A.	ram and rom
B.	ram and secondary memory
C.	processor and ram
D.	none of the mentioned
Answer» C. processor and ram

Discussion

30.	For converting a virtual address into the physical address, the programs are divided into
A.	pages
B.	frames
C.	segments
D.	blocks
Answer» B. frames

Discussion

31.	The memory allocated to each page is contiguous.
A.	true
B.	false
Answer» B. false

Discussion

32.	Which of the architecture is power efficient?
A.	cisc
B.	risc
C.	isa
D.	iana
Answer» C. isa

Discussion

33.	In CISC architecture most of the complex instructions are stored in
A.	register
B.	diodes
C.	cmos
D.	transistors
Answer» E.

Discussion

34.	Pipe-lining is a unique feature of
A.	risc
B.	cisc
C.	isa
D.	iana
Answer» B. cisc

Discussion

35.	Both the CISC and RISC architectures have been developed to reduce the
A.	cost
B.	time delay
C.	semantic gap
D.	all of the mentioned
Answer» D. all of the mentioned

Discussion

36.	The iconic feature of the RISC machine among the following is
A.	reduced number of addressing modes
B.	increased memory size
C.	having a branch delay slot
D.	all of the mentioned
Answer» D. all of the mentioned

Discussion

37.	The RISC processor has a more complicated design than CISC.
A.	true
B.	false
Answer» C.

Discussion

38.	The Sun micro systems processors usually follow Â Â Â Â Â Â Â Â Â Â Â architecture.
A.	cisc
B.	isa
C.	ultra sparc
D.	risc
Answer» E.

Discussion

39.	The computer architecture aimed at reducing the time of execution of instructions is
A.	cisc
B.	risc
C.	isa
D.	anna
Answer» C. isa

Discussion

40.	The CISC stands for
A.	computer instruction set compliment
B.	complete instruction set compliment
C.	computer indexed set components
D.	complex instruction set computer
Answer» E.

Discussion

41.	The commitment unit uses a queue called
A.	record buffer
B.	commitment buffer
C.	storage buffer
D.	none of the mentioned
Answer» B. commitment buffer

Discussion

42.	A special unit used to govern the out of order execution of the instructions is called as
A.	commitment unit
B.	temporal unit
C.	monitor
D.	supervisory unit
Answer» B. temporal unit

Discussion

43.	The step where in the results stored in the temporary register is transferred into the permanent register is called as
A.	final step
B.	commitment step
C.	last step
D.	inception step
Answer» C. last step

Discussion

44.	Since it uses the out of order mode of execution, the results are stored in
A.	buffers
B.	special memory locations
C.	temporary registers
D.	tlb
Answer» D. tlb

Discussion

45.	In super-scalar mode, all the similar instructions are grouped and executed together.
A.	true
B.	false
Answer» B. false

Discussion

46.	If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have
A.	exception handling
B.	imprecise exceptions
C.	error correction
D.	none of the mentioned
Answer» C. error correction

Discussion

47.	When the processor executes multiple instructions at a time it is said to use
A.	single issue
B.	multiplicity
C.	visualization
D.	multiple issues
Answer» E.

Discussion

48.	The throughput of a super scalar processor is
A.	less than 1
B.	1
C.	more than 1
D.	not known
Answer» D. not known

Discussion

49.	If a unit completes its task before the allotted time period, then
A.	special memory locations
B.	special purpose registers
C.	cache
D.	buffers
Answer» D. buffers

Discussion

50.	The Â Â Â Â Â Â Â Â Â Â Â Â Â Â plays a very vital role in case of super scalar processors.
A.	compilers
B.	motherboard
C.	memory
D.	peripherals
Answer» B. motherboard

Discussion

Explore topic-wise MCQs in Testing Subject.

The 68000 uses Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â method to access I/O devices buffers.

The instructions in 68000 can deal with operands of three different sizes.

Instructions which can handle any type of addressing mode are said to be

The addresses generated by the 68000 is Â Â Â Â Â Â Â Â Â Â Â bit.

The 68000 uses Â Â Â Â Â Â Â Â Â Â Â address assignment.

When an operand is stored in a register it is

The 68000 has a max of how many data registers?

Is 68000 computer Byte addressable?

The register in 68000 can contain up to Â Â Â Â Â Â Â Â Â Â Â bits.

The general purpose registers are combined into a block called as

Whenever a request to the page that is not present in the main memory is accessed Â Â Â Â Â Â Â Â Â Â Â Â Â Â is triggered.

The word length in the 68000 computer is

Â Â Â Â Â Â Â Â Â Â Â register is designated to point to the 68000 processor stack.

What does the RUN signal do?

The TLB is incorporated as part of the

When the page table is placed in the main memory, the Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â is used to store the recently accessed pages.

If the page table is large then it is stored in

The page table should be ideally situated within

The bit used to store whether the page has been modified or not is called as

The bits used to indicate the status of the page in the memory is called

The Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â bit is used to indicate the validity of the page.

The starting address of the page table is stored in

The area in the main memory that can hold one page is called as

The lower order bits of the virtual address forms the

The higher order bits of the virtual address generated by the processor forms the

The cache bridges the speed gap between Â Â Â Â Â Â Â Â Â Â Â Â Â Â and

The pages size shouldnâ€™t be too small, as this would lead to

The page length shouldnâ€™t be too long because

The virtual memory bridges the size and speed gap between Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â and

For converting a virtual address into the physical address, the programs are divided into

The memory allocated to each page is contiguous.

Which of the architecture is power efficient?

In CISC architecture most of the complex instructions are stored in

Pipe-lining is a unique feature of

Both the CISC and RISC architectures have been developed to reduce the

The iconic feature of the RISC machine among the following is

The RISC processor has a more complicated design than CISC.

The Sun micro systems processors usually follow Â Â Â Â Â Â Â Â Â Â Â architecture.

The computer architecture aimed at reducing the time of execution of instructions is

The CISC stands for

The commitment unit uses a queue called

A special unit used to govern the out of order execution of the instructions is called as

The step where in the results stored in the temporary register is transferred into the permanent register is called as

Since it uses the out of order mode of execution, the results are stored in

In super-scalar mode, all the similar instructions are grouped and executed together.

If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have

When the processor executes multiple instructions at a time it is said to use

The throughput of a super scalar processor is

If a unit completes its task before the allotted time period, then

The Â Â Â Â Â Â Â Â Â Â Â Â Â Â plays a very vital role in case of super scalar processors.