Explore topic-wise MCQs in Computer Organization.

This section includes 585 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Organization knowledge and support exam preparation. Choose a topic below to get started.

501.

Physical memory is divided into sets of finite size called as ___

A. Frames
B. Pages
C. Blocks
D. Vectors
Answer» B. Pages
502.

During transfer of data between the processor and memory we use ___

A. Cache
B. TLB
C. Buffers
D. Registers
Answer» E.
503.

____ method is used to map logical addresses of variable length onto physical memory.

A. Paging
B. Overlays
C. Segmentation
D. Paging with segmentation
Answer» D. Paging with segmentation
504.

To get the physical address from the logical address generated by CPU we use _

A. MAR
B. MMU
C. Overlays
D. TLB
Answer» C. Overlays
505.

When using the Big Endian assignment to store a number, the sign bit of the number is stored in __

A. The higher order byte of the word
B. The lower order byte of the word
C. Can’t say
D. None of the mentioned
Answer» B. The lower order byte of the word
506.

The type of memory assignment used in Intel processors is ___

A. Little Endian
B. Big Endian
C. Medium Endian
D. None of the mentioned
Answer» B. Big Endian
507.

If a system is 64 bit machine , then the length of each word will be __

A. 4 bytes
B. 8 bytes
C. 16 bytes
D. 12 bytes
Answer» C. 16 bytes
508.

In the implementation of a Multiplier circuit in the system we make use of _

A. Counter
B. Flip flop
C. Shift register
D. Push down stack
Answer» D. Push down stack
509.

The collection of the above mentioned entities where data is stored is called as

A. Block
B. Set
C. Word
D. Byte
Answer» D. Byte
510.

The smallest entity of memory is called as __

A. Cell
B. Block
C. Instance
D. Unit
Answer» B. Block
511.

When 1101 is used to divide 100010010 the remainder is __

A. 101
B. 11
C. 0
D. 1
Answer» E.
512.

In some pipelined systems, a different instruction is used to add to numbers which can affect the flags upon execution. That instruction is __

A. AddSetCC
B. AddCC
C. Add++
D. SumSetCC
Answer» B. AddCC
513.

In a normal n-bit adder, to find out if an overflow as occured we make use of ___

A. And gate
B. Nand gate
C. Nor gate
D. Xor gate
Answer» E.
514.

For the addition of large integers most of the systems make use of _

A. Fast adders
B. Full adders
C. Carry look-ahead adders
D. None of the mentioned
Answer» D. None of the mentioned
515.

The most efficient method followed by computers to multiply two unsigned numbers is _____

A. Booth algorithm
B. Bit pair recording of multipliers
C. Restoring algorithm
D. Non restoring algorithm
Answer» C. Restoring algorithm
516.

The Flag ‘V’ is set to 1 indicates that,

A. The operation is valid
B. The operation is validated
C. The operation as resulted in an overflow
D. None of the mentioned
Answer» D. None of the mentioned
517.

The register used to store the flags is called as ____

A. Flag register
B. Status register
C. Test register
D. Log register
Answer» C. Test register
518.

The processor keeps track of the results of its operations using a flags called __

A. Conditional code flags
B. Test output flags
C. Type flags
D. None of the mentioned
Answer» B. Test output flags
519.

When we subtract -3 from 2 , the answer in 2’s compliment form is ___

A. 0001
B. 1101
C. 0101
D. 1001
Answer» D. 1001
520.

When we perform subtraction on -7 and -5 the answer in 2’s compliment form is __

A. 11110
B. 1110
C. 1010
D. 0010
Answer» C. 1010
521.

When we perform subtraction on -7 and 1 the answer in 2’s compliment form is _

A. 1010
B. 1110
C. 0110
D. 1000
Answer» E.
522.

Which representation is most efficient to perform arithmetic operations on the numbers ?

A. Sign-magnitude
B. 1’s compliment
C. 2’S compliment
D. None of the mentioned
Answer» D. None of the mentioned
523.

Which method/s of representation of numbers occupies large amount of memory than others ?

A. Sign-magnitude
B. 1’s compliment
C. 2’s compliment
D. 1’s & 2’s compliment
Answer» B. 1’s compliment
524.

Which method of representation has two representations for ‘0’ ?

A. Sign-magnitude
B. 1’s compliment
C. 2’s compliment
D. None of the mentioned
Answer» B. 1’s compliment
525.

___ addressing mode is most suitable to change the normal sequence of execution of instructions.

A. Relative
B. Indirect
C. Index with Offset
D. Immediate
Answer» B. Indirect
526.

The effective address of the following instruction is, MUL 5(R1,R2).

A. 5+R1+R2
B. 5+(R1*R2)
C. 5+[R1]+[R2].
D. 5*([R1]+[R2])
Answer» D. 5*([R1]+[R2])
527.

The addressing mode, where you directly specify the operand value is __

A. Immediate
B. Direct
C. Definite
D. Relative
Answer» B. Direct
528.

In the following indexed addressing mode instruction, MOV 5(R1),LOC the effective address is _

A. EA = 5+R1
B. EA = R1
C. EA = [R1] d) EA = 5+[R1]
D. None of above
Answer» E.
529.

The addressing mode which makes use of in-direction pointers is __

A. Indirect addressing mode
B. Index addressing mode
C. Relative addressing mode
D. Offset addressing mode
Answer» B. Index addressing mode
530.

Add #45, when this instruction is executed the following happen/s ___

A. The processor raises an error and requests for one more operand
B. The value stored in memory location 45 is retrieved and one more operand is requested
C. The value 45 gets added to the value on the stack and is pushed onto the stack
D. None of the mentioned
Answer» C. The value 45 gets added to the value on the stack and is pushed onto the stack
531.

In case of, Zero-address instruction method the operands are stored in __

A. Registers
B. Accumulators
C. Push down stack
D. Cache
Answer» D. Cache
532.

The instruction, Add #45,R1 does __

A. Adds the value of 45 to the address of R1 and stores 45 in that address
B. Adds 45 to the value of R1 and stores it in R1
C. Finds the memory location 45 and adds that content to that of R1
D. None of the mentioned
Answer» C. Finds the memory location 45 and adds that content to that of R1
533.

CISC stands for _

A. Complete Instruction Sequential Compilation
B. Computer Integrated Sequential Compiler
C. Complex Instruction Set Computer
D. Complex Instruction Sequential Compilation
Answer» D. Complex Instruction Sequential Compilation
534.

If the instruction, Add R1, R2, R3 is executed in a system which is pipe-lined, then the value of S is (Where S is term of the Basic performance equation)

A. 3
B. ~2
C. ~1
D. 6
Answer» D. 6
535.

The clock rate of the processor can be improved by __

A. Improving the IC technology of the logic circuits
B. Reducing the amount of processing done in one step
C. By using overclocking method
D. All of the mentioned
Answer» E.
536.

The average number of steps taken to execute the set of instructions can be made to be less than one by following _____

A. ISA
B. Pipe-lining
C. Super-scaling
D. Sequential
Answer» D. Sequential
537.

When Performing a looping operation, the instruction gets stored in the __

A. Registers
B. Cache
C. System Heap
D. System stack
Answer» C. System Heap
538.

As of 2000, the reference system to find the performance of a system is __

A. Ultra SPARC 10
B. SUN SPARC
C. SUN II
D. None of the mentioned
Answer» B. SUN SPARC
539.

SPEC stands for __

A. Standard Performance Evaluation Code
B. System Processing Enhancing Code
C. System Performance Evaluation Corporation
D. Standard Processing Enhancement Corporation
Answer» D. Standard Processing Enhancement Corporation
540.

The ultimate goal of a compiler is to _

A. Reduce the clock cycles for a programming task
B. Reduce the size of the object code
C. Be versatile
D. Be able to detect even the smallest of errors
Answer» B. Reduce the size of the object code
541.

An optimizing Compiler does __

A. Better compilation of the given piece of code
B. Takes advantage of the type of processor and reduces its process time
C. Does better memory managament
D. none of the mentioned
Answer» C. Does better memory managament
542.

For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution ?

A. ISA
B. ANSA
C. Super-scalar
D. All of the mentioned
Answer» D. All of the mentioned
543.

A processor performing fetch or decoding of different instruction during the execution of another instruction is called ____

A. Super-scaling
B. Pipe-lining
C. Parallel Computation
D. None of the mentioned
Answer» C. Parallel Computation
544.

Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster ?

A. A
B. B
C. Both take the same time
D. Insuffient information
Answer» B. B
545.

During the execution of the instructions, a copy of the instructions is placed in the ___

A. Register
B. RAM
C. System heap
D. Cache
Answer» E.
546.

The ISA standard Buses are used to connect ___

A. RAM and processor
B. GPU and processor
C. Harddisk and Processor
D. CD/DVD drives and Processor
Answer» D. CD/DVD drives and Processor
547.

The main advantage of multiple bus organisation over single bus is __

A. Reduction in the number of cycles for execution
B. Increase in size of the registers
C. Better Connectivity
D. None of the mentioned
Answer» B. Increase in size of the registers
548.

In multiple Bus organisation, the registers are collectively placed and referred as _

A. Set registers
B. Register file
C. Register Block
D. Map registers
Answer» C. Register Block
549.

___ register Connected to the Processor bus is a single-way transfer capable.

A. PC
B. IR
C. Temp
D. Z
Answer» E.
550.

ANSI stands for _

A. American National Standards Institute
B. American National Standard Interface
C. American Network Standard Interfacing
D. American Network Security Interrupt
Answer» B. American National Standard Interface