MCQOPTIONS
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MCQOPTIONS
This section includes 657 Mcqs, each offering curated multiple-choice questions to sharpen your Testing Subject knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
IBM developed a bus standard for their line of computers ‘PC AT’ called ___ |
| A. | IB bus |
| B. | M-bus |
| C. | ISA |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 2. |
The bus used to connect the monitor to the CPU is __ |
| A. | PCI bus |
| B. | SCSI bus |
| C. | Memory bus |
| D. | Rambus |
| Answer» C. Memory bus | |
| 3. |
To extend the connectivity of the processor bus we use _ |
| A. | PCI bus |
| B. | SCSI bus |
| C. | Controllers |
| D. | Multiple bus |
| Answer» B. SCSI bus | |
| 4. |
The registers,ALU and the interconnection between them are collectively called as _ |
| A. | process route |
| B. | information trail |
| C. | information path |
| D. | data path |
| Answer» E. | |
| 5. |
___ are used to over come the difference in data transfer speeds of various devices. |
| A. | Speed enhancing circuitory |
| B. | Bridge circuits |
| C. | Multiple Buses |
| D. | Buffer registers |
| Answer» E. | |
| 6. |
The main virtue for using single Bus structure is ____ |
| A. | Fast data transfers |
| B. | Cost effective connectivity and speed |
| C. | Cost effective connectivity and ease of attaching peripheral devices |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 7. |
______ is used to store data in registers. |
| A. | D flip flop |
| B. | JK flip flop |
| C. | RS flip flop |
| D. | None of the mentioned |
| Answer» B. JK flip flop | |
| 8. |
___ is used to choose between incrementing the PC or performing ALU operations. |
| A. | Conditional codes |
| B. | Multiplexer |
| C. | Control unit |
| D. | None of the mentioned |
| Answer» C. Control unit | |
| 9. |
The internal Components of the processor are connected by ___ |
| A. | Processor intra-connectivity circuitry |
| B. | Processor bus |
| C. | Memory bus |
| D. | Rambus |
| Answer» C. Memory bus | |
| 10. |
ISP stands for ___ |
| A. | Instruction Set Processor |
| B. | Information Standard Processing |
| C. | Interchange Standard Protocol |
| D. | Interrupt Service Procedure |
| Answer» B. Information Standard Processing | |
| 11. |
The decoded instruction is stored in _____ |
| A. | IR |
| B. | PC |
| C. | Registers |
| D. | MDR |
| Answer» B. PC | |
| 12. |
The time delay between two successive initiation of memory operation _ |
| A. | Memory access time |
| B. | Memory search time |
| C. | Memory cycle time |
| D. | Instruction delay |
| Answer» D. Instruction delay | |
| 13. |
MFC stands for _________ |
| A. | Memory Format Caches |
| B. | Memory Function Complete |
| C. | Memory Find Command |
| D. | Mass Format Command |
| Answer» C. Memory Find Command | |
| 14. |
_____ is generally used to increase the apparent size of physical memory. |
| A. | Secondary memory |
| B. | Virtual memory |
| C. | Hard-disk |
| D. | Disks |
| Answer» C. Hard-disk | |
| 15. |
The I/O interface required to connect the I/O device to the bus consists of _ |
| A. | Address decoder and registers |
| B. | Control circuits |
| C. | Address decoder, registers and Control circuits |
| D. | Only Control circuits |
| Answer» D. Only Control circuits | |
| 16. |
To reduce the memory access time we generally make use of __ |
| A. | Heaps |
| B. | Higher capacity RAM’s |
| C. | SDRAM’s |
| D. | Cache’s |
| Answer» E. | |
| 17. |
____ bus structure is usually used to connect I/O devices. |
| A. | Single bus |
| B. | Multiple bus |
| C. | Star bus |
| D. | Rambus |
| Answer» B. Multiple bus | |
| 18. |
The Input devices can send information to the processor. |
| A. | When the SIN status flag is set |
| B. | When the data arrives regardless of the SIN flag |
| C. | Neither of the cases |
| D. | Either of the cases |
| Answer» B. When the data arrives regardless of the SIN flag | |
| 19. |
The small extremely fast, RAM’s are called as __ |
| A. | Cache |
| B. | Heaps |
| C. | Accumulators |
| D. | Stacks |
| Answer» B. Heaps | |
| 20. |
_____ are numbers and encoded characters, generally used as operands. |
| A. | Input |
| B. | Data |
| C. | Information |
| D. | Stored Values |
| Answer» C. Information | |
| 21. |
The ALU makes use of _______ to store the intermediate results. |
| A. | Accumulators |
| B. | Registers |
| C. | Heap |
| D. | Stack |
| Answer» B. Registers | |
| 22. |
The control unit controls other units by generating __ |
| A. | Control signals |
| B. | Timing signals |
| C. | Transfer signals |
| D. | Command Signals |
| Answer» C. Transfer signals | |
| 23. |
A source program is usually in _ |
| A. | Assembly language |
| B. | Machine level language |
| C. | High-level language |
| D. | Natural language |
| Answer» D. Natural language | |
| 24. |
The 8-bit encoding format used to store data in a computer is _____ |
| A. | ASCII |
| B. | EBCDIC |
| C. | ANCI |
| D. | USCII |
| Answer» C. ANCI | |
| 25. |
The ______ format is usually used to store data. |
| A. | BCD |
| B. | Decimal |
| C. | Hecadecimal |
| D. | Octal |
| Answer» B. Decimal | |
| 26. |
THE_REGISTERS,_ALU_AND_THE_INTERCONNECTION_BETWEEN_THEM_ARE_COLLECTIVELY_CALLED_AS______?$ |
| A. | process route |
| B. | information trail |
| C. | information path |
| D. | data path |
| Answer» E. | |
| 27. |
________is_used_to_store_data_in_registers.$ |
| A. | D flip flop |
| B. | JK flip flop |
| C. | RS flip flop |
| D. | None of the mentioned |
| Answer» B. JK flip flop | |
| 28. |
______ is used to choose between incrementing the PC or performing ALU operations? |
| A. | Conditional codes |
| B. | Multiplexer |
| C. | Control unit |
| D. | None of the mentioned |
| Answer» C. Control unit | |
| 29. |
The internal Components of the processor are connected by _______ |
| A. | Processor intra-connectivity circuitry |
| B. | Processor bus |
| C. | Memory bus |
| D. | Rambus |
| Answer» C. Memory bus | |
| 30. |
ISP stands for _________ |
| A. | Instruction Set Processor |
| B. | Information Standard Processing |
| C. | Interchange Standard Protocol |
| D. | Interrupt Service Procedure |
| Answer» B. Information Standard Processing | |
| 31. |
Which of the register/s of the processor is/are connected to Memory Bus? |
| A. | PC |
| B. | MAR |
| C. | IR |
| D. | Both PC and MAR |
| Answer» C. IR | |
| 32. |
During the execution of a program which gets initialized first? |
| A. | MDR |
| B. | IR |
| C. | PC |
| D. | MAR |
| Answer» D. MAR | |
| 33. |
Which registers can interact with the secondary storage? |
| A. | MAR |
| B. | PC |
| C. | IR |
| D. | R0 |
| Answer» B. PC | |
| 34. |
The instruction -> Add LOCA, R0 does _______ |
| A. | Adds the value of LOCA to R0 and stores in the temp register |
| B. | Adds the value of R0 to the address of LOCA |
| C. | Adds the values of both LOCA and R0 and stores it in R0 |
| D. | Adds the value of LOCA with a value in accumulator and stores it in R0 |
| Answer» D. Adds the value of LOCA with a value in accumulator and stores it in R0 | |
| 35. |
The decoded instruction is stored in ______ |
| A. | IR |
| B. | PC |
| C. | Registers |
| D. | MDR |
| Answer» B. PC | |