MCQOPTIONS
Saved Bookmarks
This section includes 10 Mcqs, each offering curated multiple-choice questions to sharpen your Linear Integrated Circuit knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
CMOS_INVERTER_IS_USED_AS_SPDT_SWITCH_IN_RESISTOR_DAC_AND_IS_CONNECTED_TO_THE_OP-AMP_LINE._FIND_THE_OUTPUT_OF_CMOS,_IF_THE_INPUT_APPLIED_IS_1?$ |
| A. | Resistance is connected to ground |
| B. | Resistance is connected to input line |
| C. | Resistance is connected to bit line |
| D. | None of the mentioned |
| Answer» B. Resistance is connected to input line | |
| 2. |
THE_SMALLEST_RESISTOR_IN_A_12_BIT_WEIGHTED_RESISTOR_DAC_IS_2.5K‚ÂÀ√≠¬¨¬©,_WHAT_WILL_BE_THE_LARGEST_RESISTOR_VALUE??$# |
| A. | 40.96MΩ |
| B. | 10.24MΩ |
| C. | 61.44 MΩ |
| D. | 18.43MΩ |
| Answer» C. 61.44 M‚âà√≠¬¨¬© | |
| 3. |
How to overcome the limitation of binary weighted resistor type DAC?$ |
| A. | Using R-2R ladder type DAC |
| B. | Multiplying DACs |
| C. | Using monolithic DAC |
| D. | Using hybrid DAC |
| Answer» D. Using hybrid DAC | |
| 4. |
What is the disadvantage of binary weighted type DAC? |
| A. | Require wide range of resistors |
| B. | High operating frequency |
| C. | High power consumption |
| D. | Slow switching |
| Answer» C. High power consumption | |
| 5. |
Pick out the incorrect statement “In a 3 bit weighted resistor DAC”$ |
| A. | Although the op-amp is connected in inverting mode, it can also be connected in non-inverting mode |
| B. | The op-amp simply work as a current to voltage converter |
| C. | The polarity of the reference voltage is chosen in accordance with the input voltage |
| D. | None of the mentioned |
| Answer» B. The op-amp simply work as a current to voltage converter | |
| 6. |
Determine the Full scale output in a 8-bit DAC for 0-15v range? |
| A. | Full scale output=15.1v |
| B. | Full scale output=15.2v |
| C. | Full scale output=14.5v |
| D. | Full scale output=14.94v |
| Answer» D. Full scale output=14.94v | |
| 7. |
In a D-A converter with binary weighted resistor, a desired step size can be obtained by |
| A. | Selecting proper value of V<sub>FS</sub> |
| B. | Selecting proper value of R |
| C. | Selecting proper value of R<sub>F</sub> |
| D. | All of the mentioned |
| Answer» E. | |
| 8. |
(VR/R )× (do/2 +d1/22 + ……dn/2n)$ |
| A. | (V<sub>R</sub>/R )× (d<sub>1</sub>/2<sup>1</sup> +d<sub>2</sub>/2<sup>2</sup> + ……d<sub>n</sub>/2<sup>n</sup>) |
| B. | (V<sub>R</sub>/R )× (d<sub>0</sub><sup>2</sup>/2 +d<sub>1</sub><sup>2</sup>/2<sup>2</sup> + ……d<sub>n</sub><sup>2</sup>/2<sup>n</sup>) |
| C. | None of the mentioned |
| Answer» D. | |
| 9. |
Why the switches used in weighted resistor DAC are of single pole double throw (SPDT) type? |
| A. | To connect the resistance to reference voltage |
| B. | To connect the resistance to ground |
| C. | To connect the resistance to either reference voltage or ground |
| D. | To connect the resistance to output |
| Answer» D. To connect the resistance to output | |
| 10. |
Express the output voltage of digital to analog converter? |
| A. | V<sub>o</sub> =KV<sub>FS</sub>(d<sub>1</sub>2<sup>-1</sup>+d<sub>2</sub>2<sup>-2</sup>+….d<sub>n</sub>2<sup>-n</sup>) |
| B. | V<sub>o</sub> =V<sub>FS</sub>/k(d<sub>1</sub>2<sup>-1</sup>+d<sub>2</sub>2<sup>-2</sup>+….d<sub>n</sub>2<sup>-n</sup>) |
| C. | V<sub>o</sub> =V<sub>FS</sub>(d<sub>1</sub>2<sup>-1</sup>+d<sub>2</sub>2<sup>-2</sup>+….d<sub>n</sub>2<sup>-n</sup>) |
| D. | V<sub>o</sub> =K(d<sub>1</sub>2<sup>-1</sup>+d<sub>2</sub>2<sup>-2</sup>+….d<sub>n</sub>2<sup>-n</sup>) |
| Answer» B. V<sub>o</sub> =V<sub>FS</sub>/k(d<sub>1</sub>2<sup>-1</sup>+d<sub>2</sub>2<sup>-2</sup>+‚Äö√Ñ√∂‚àö√묨‚àÇ.d<sub>n</sub>2<sup>-n</sup>) | |