MCQOPTIONS
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MCQOPTIONS
This section includes 13 Mcqs, each offering curated multiple-choice questions to sharpen your Linear Integrated Circuit knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
STATE_THE_CORRECT_REASON_FOR_NEGLECTING_PNP_TRANSISTOR.?$ |
| A. | Increase in the series collector resistance of pnp transistor |
| B. | Parasitic capacitance appears between collector and substrate |
| C. | Current gain of pnp transistor is as low as 1.5 to 30 |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 2. |
The advantage of Multi-emitter transistor is$ |
| A. | To reduce fabrication steps |
| B. | To save chip area |
| C. | To lower design consideration |
| D. | To provide linear output |
| Answer» C. To lower design consideration | |
| 3. |
The diffusion of collector impurities in npn transistor should be small because,$ |
| A. | No additional diffusion or masking steps required |
| B. | Bandwidth is controlled by lateral diffusion of p-type impurity |
| C. | Collector need not be kept at negative potential |
| D. | None of the mentioned |
| Answer» E. | |
| 4. |
Choose the appropriate value of diode to get a speedy diode from the given values of storage time (n) in sec and forward voltage (V γ).$ |
| A. | n = 56 , V<sub> γ</sub> = 0.96 |
| B. | n = 100 , V<sub> γ</sub> = 0.92 |
| C. | n = 9 , V<sub> γ</sub> = 0.85 |
| D. | n = 53 , V<sub> γ</sub> = 0.95 |
| Answer» D. n = 53 , V<sub> ‚âà√≠‚Äö√¢‚Ä¢</sub> = 0.95 | |
| 5. |
Which transistor is best suitable to achieve very fast switching in digital circuits? |
| A. | Lateral pnp transistor |
| B. | Schottky transistor |
| C. | Multi-emitter transistor |
| D. | NPN transistor |
| Answer» C. Multi-emitter transistor | |
| 6. |
Which method is used in the fabrication of pnp transistor? |
| A. | Vertical substrate pnp |
| B. | Triple diffused pnp |
| C. | Lateral pnp |
| D. | All of the mentioned |
| Answer» E. | |
| 7. |
At what potential, the substrate of a vertical pnp transistor should be kept to attain good isolation? |
| A. | Same potential |
| B. | Positive potential |
| C. | Different potential |
| D. | Negative potential |
| Answer» E. | |
| 8. |
The ‘buried layer’ reduces collector series resistance by providing,$ |
| A. | A low resistivity current path from n-type layer to n<sup>+</sup> contact layer |
| B. | A low resistivity current path from p-type layer to n<sup>+</sup> contact layer |
| C. | A high resistivity current path from n-type layer to n<sup>+</sup> contact layer |
| D. | A high resistivity current path from p-type layer to n<sup>+</sup> contact layer |
| Answer» B. A low resistivity current path from p-type layer to n<sup>+</sup> contact layer | |
| 9. |
Which of the following transistor has the limitation, due to the requirement of additional fabrication steps and design consideration? |
| A. | Vertical pnp transistor |
| B. | Lateral pnp transistor |
| C. | Triple diffused pnp transistor |
| D. | Substrate pnp transistor |
| Answer» D. Substrate pnp transistor | |
| 10. |
What is the reason for using Lateral pnp transistor in Integrated Circuits? |
| A. | Requires simple process control |
| B. | Simultaneous fabrication of pnp and npn transistors |
| C. | Provide good isolation |
| D. | Miniaturization and cost reduction |
| Answer» C. Provide good isolation | |
| 11. |
Name the process that is used to overcome the increase in collector series resistance, which occurs due to the presence of collector contact at the top of integrated transistor. |
| A. | Buried n<sup>+</sup> layer |
| B. | Buried p<sup>+</sup> layer |
| C. | Triple diffused layer |
| D. | Buried epitaxial layer |
| Answer» B. Buried p<sup>+</sup> layer | |
| 12. |
Why monolithic IC transistor is preferred over discrete planar epitaxial transistor? |
| A. | Due to structural difference |
| B. | Increase in V<sub>CE</sub> (sat) and collector series resistor |
| C. | Improvement in circuit performance |
| D. | All of the mentioned |
| Answer» E. | |
| 13. |
Which is the most striking feature in monolithic integrated circuit transistor? |
| A. | Collector contact is present at the bottom of IC |
| B. | Collector contact is present at the top of IC |
| C. | Collector contact is absent |
| D. | Collector contact is present on one of the sides of IC |
| Answer» C. Collector contact is absent | |