MCQOPTIONS
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MCQOPTIONS
This section includes 657 Mcqs, each offering curated multiple-choice questions to sharpen your Testing Subject knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
A single instruction to clear the lower four bits of the accumulator in 8085 assembly language is |
| A. | XRI OFH |
| B. | ANI FOH |
| C. | XRI FOH |
| D. | ANI OFH |
| Answer» C. XRI FOH | |
| 2. |
An Assembler for a micro-processor is used for |
| A. | assembly of processors in a production line |
| B. | creation of new programmes using different modules |
| C. | translation of a program from assembly language to machine language |
| D. | translation of a higher level language into English text |
| Answer» D. translation of a higher level language into English text | |
| 3. |
The chip select access time for reading ROM contents is |
| A. | the delay between application of proper chip select signal and the stable output address |
| B. | the delay between the previous valid output data and the next change in address |
| C. | the time for which the output data remains valid when the device is no longer selected |
| D. | maximum time for which the valid address can be changed |
| Answer» B. the delay between the previous valid output data and the next change in address | |
| 4. |
Consider the following set of instructions: |
| A. | doubles the number in Register by B |
| B. | divides the number in Register by 2 |
| C. | multiples B by A |
| D. | adds A and B |
| Answer» C. multiples B by A | |
| 5. |
A personal computer has typically |
| A. | 5 to 10 kilobytes of main memory |
| B. | 10 to 100 kilobytes of main memory |
| C. | 100 to 256 kilobytes of main memory |
| D. | 256 kilobytes to 1 megabyte of main memory. |
| Answer» E. | |
| 6. |
The TRAP is one of the interrupts available in INTEL 8085. Which one of the following statements is true of TRAP? |
| A. | It is level triggered |
| B. | It is negative edge triggered |
| C. | It is positive edge triggered |
| D. | It is both positive edge triggered and level triggered |
| Answer» E. | |
| 7. |
If instruction RST is written in a program the problem will jump to location |
| A. | 0020 H |
| B. | 0024 H |
| C. | 0028 H |
| D. | 002 CH |
| Answer» D. 002 CH | |
| 8. |
An interrupt in which the external device supplies its address as well as the interrupt request, is known as |
| A. | vectored interrupt |
| B. | maskable interrupt |
| C. | polled interrupt |
| D. | non-maskable interrupt |
| Answer» D. non-maskable interrupt | |
| 9. |
The maximum integer which can be stored on an 8-bit accumulator is_______ |
| A. | 260 |
| B. | 255 |
| C. | 260 |
| D. | 300 |
| Answer» C. 260 | |
| 10. |
The register which holds address of the location to or from which data are to be transferred is known as |
| A. | index register |
| B. | instruction register |
| C. | memory address register |
| D. | memory data register |
| Answer» D. memory data register | |
| 11. |
The register which contains the instruction to be executed is called |
| A. | instruction register |
| B. | index register |
| C. | memory address register |
| D. | memory data register |
| Answer» C. memory address register | |
| 12. |
In a 8-bit microprocessor, the fetch cycle required to fetch a 8 byte instruction will be |
| A. | 1 |
| B. | 2 |
| C. | 5 |
| D. | depends on computer design |
| Answer» E. | |
| 13. |
An instruction cycle is made up of |
| A. | one or more execute cycles |
| B. | one or more fetch cycles |
| C. | one opcode and one execute cycle |
| D. | none of these |
| Answer» B. one or more fetch cycles | |
| 14. |
Following program is written for an 8085 microprocessor to add two bytes located at memory addresses 1FFE and 1FFF |
| A. | in the register A |
| B. | at the memory address 1000 |
| C. | at the memory address 1F00 |
| D. | at the memory address 2000 |
| Answer» E. | |
| 15. |
In a 8-bit microcomputer having 8K bytes of RAM memory, the length of SP will be_______ |
| A. | 12 |
| B. | 11 |
| C. | 10 |
| D. | 13 |
| Answer» E. | |
| 16. |
The minimum number of operations required in a micro-processor with 8 data pins to read a 32-bit word |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» E. | |
| 17. |
The address bus of inlet 8085 is 16 bit wide and hence the memory which can be accessed by this address bus is________KB |
| A. | 60 |
| B. | 62 |
| C. | 64 |
| D. | 66 |
| Answer» D. 66 | |
| 18. |
The number of minimum clock cycles in a machine cycle for 8085 are_____ |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» D. 4 | |
| 19. |
The ____ number of address lines are needed to address each memory location in a 2048 4 memory chip |
| A. | 12 |
| B. | 12 |
| C. | 13 |
| D. | 11 |
| Answer» E. | |
| 20. |
The highest priority in 8085 micropr ocessor system is |
| A. | RST 7.5 |
| B. | RST 6.5 |
| C. | INTR |
| D. | TRAP |
| Answer» E. | |
| 21. |
In a 8085 microprocessor, the following sequence of instructions is executed: |
| A. | rotate the contents of the accumulator and store it in B |
| B. | get the contents of B register into accumulator and rotate it to left by one bit |
| C. | double contents of B register |
| D. | manipulate carry in A and B |
| Answer» D. manipulate carry in A and B | |
| 22. |
The larger the RAM of a computer, the faster is its speed, since it eliminates |
| A. | need for ROM |
| B. | need for external memory |
| C. | frequent disk I/Os |
| D. | need for a data-wide path |
| Answer» D. need for a data-wide path | |
| 23. |
In an 8085 microprocesser system, the RST instruction will cause an interrupt |
| A. | only if an interrupt service routine is not being executed |
| B. | only if a bit in the interrupt mask is made 0 |
| C. | only if interrupts have been enabled by an EI instruction |
| D. | none of these |
| Answer» D. none of these | |
| 24. |
Number of machine cycles required for RET instruction in 8085 microprocessor is |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 5 |
| E. | 7 |
| Answer» D. 5 | |
| 25. |
A ROM is used to store the table for multiplication of two 8-bit unsigned integers. The size of ROM required is |
| A. | 256 16 |
| B. | 16K 8 |
| C. | 4K 16 |
| D. | 64K 16 |
| Answer» E. | |
| 26. |
As compared to 16-bit microprocessor, 8 bit microprocessor are limited in |
| A. | speed |
| B. | directly addressable memory |
| C. | data handling capability |
| D. | all of these |
| Answer» E. | |
| 27. |
Intel 8080A and Motorola 6800 microprocessor differ in |
| A. | number of address lines |
| B. | number of data lines |
| C. | instruction set |
| D. | instruction set and operating frequency |
| Answer» E. | |
| 28. |
In 8085 Program Status Word consists of |
| A. | accumulator contents |
| B. | flags |
| C. | both accumulator and flag |
| D. | status bits |
| Answer» D. status bits | |
| 29. |
A microprocessor is called an n-bit microprocessor depending on |
| A. | register s length |
| B. | size of internal data bus |
| C. | size of external data bus |
| D. | none of these |
| Answer» C. size of external data bus | |
| 30. |
Intel 8080A and 8085A differ in |
| A. | number of address lines |
| B. | number of data signal |
| C. | instruction set |
| D. | number of interrupt |
| Answer» E. | |
| 31. |
The synchronization between microprocessor and memory is done by |
| A. | ALE signal |
| B. | HOLD signal |
| C. | READY signal |
| D. | none of these |
| Answer» D. none of these | |
| 32. |
The set of commands which give directions to the assembler during the assembly process but are not translated into machine instructions are called |
| A. | mnemonics |
| B. | directives |
| C. | identifiers |
| D. | operands |
| Answer» C. identifiers | |
| 33. |
The advantage of using segment registers in 8086 and above microprocessors are that they |
| A. | allow the memory capacity to be 1 megabyte even though the addresses associated with the individual instructions are only 16 bits wide |
| B. | allow the instruction, data or stack portion of a program to be more than 64K bytes long by using more than one code, data or stack segment |
| C. | facilitate the use of separate memory area for a program, its data and the stack |
| D. | all of these |
| Answer» E. | |
| 34. |
An opcode |
| A. | translates a mnemonic |
| B. | instructs the CPU |
| C. | stores data |
| D. | all of these |
| Answer» C. stores data | |
| 35. |
Which of the following enables peripherals to pass a signal down the bus to the next device on the bus during polling of the device? |
| A. | DMA |
| B. | interrupt vectoring |
| C. | daisy chain |
| D. | cycle stealing |
| Answer» D. cycle stealing | |
| 36. |
The process of causing an unplanned branching operation to occur, usually initiated by external system is called |
| A. | debugging |
| B. | masking |
| C. | interrupt |
| D. | iteration |
| Answer» D. iteration | |
| 37. |
WAIT states are used |
| A. | to give slow devices additional time to put out valid data |
| B. | to insert a deliberate delay |
| C. | during I/O operation |
| D. | none of these |
| Answer» B. to insert a deliberate delay | |
| 38. |
Which of the following signal is used when a peripheral device request the microprocess to have a DMA operation? |
| A. | IO/ M |
| B. | READY |
| C. | HOLD and HLDA |
| D. | RD and WR |
| Answer» D. RD and WR | |
| 39. |
In an 8085 microprocessor, the contents of the Accumulator, after the following instructions are executed will become |
| A. | 01 H |
| B. | 0F |
| C. | F0H |
| D. | 10 H |
| Answer» E. | |
| 40. |
An input device is interfaced with Intel 8085A microprocessor as memory mapped I /O. The address of the device is 2500H. In order to input data from the device to accumul at or, the sequence of instructions will be |
| A. | <table><tr><td>LXI</td><td>H,2500H</td></tr><tr><td>MOV</td><td>A,M</td></tr></table> |
| B. | <table><tr><td>LXI</td><td>H,2500H</td></tr><tr><td>MOV</td><td>M,A</td></tr></table> |
| C. | <table><tr><td>LHLD</td><td>2500H</td></tr><tr><td>MOV</td><td>A,M</td></tr></table> |
| D. | <table><tr><td>LHLD</td><td>2500H</td></tr><tr><td>MOV</td><td>M,A</td></tr></table> |
| Answer» B. <table><tr><td>LXI</td><td>H,2500H</td></tr><tr><td>MOV</td><td>M,A</td></tr></table> | |
| 41. |
Which one of the following statements regarding the INT (interrupt) and the BRQ (but request) pins in a CPU is true? |
| A. | The BRQ pin is sampled after every instruction cycle, but the INT is sampled after every machine cycle |
| B. | Both INT and BRQ are sampled after every machine cycle |
| C. | The INT pin is sampled after every instruction cycle, but the BRQ is sampled after every machine cycle |
| D. | Both INT and BRQ are sampled after every instruction cycle |
| Answer» B. Both INT and BRQ are sampled after every machine cycle | |
| 42. |
Which of the following statements is not applicable to serial transmission of data? |
| A. | One bit at a time |
| B. | Faster method of trans-mission |
| C. | LSB transferred first |
| D. | Only one wire used |
| Answer» C. LSB transferred first | |
| 43. |
A microprocessor contains |
| A. | most of the control and arithmetic logic functions of a computer |
| B. | most of the RAM |
| C. | most of the ROM |
| D. | peripheral drivers |
| Answer» B. most of the RAM | |
| 44. |
In microprocessor |
| A. | program is stored in memory and data is stored in registers |
| B. | program is stored in registers and data is stored in memory |
| C. | both program and data are stored in memory |
| D. | both program and data are stored in registers |
| Answer» B. program is stored in registers and data is stored in memory | |
| 45. |
Intel 8085A and 8086A differ in |
| A. | number of address lines |
| B. | number of data lines |
| C. | operating frequency |
| D. | all of these |
| Answer» E. | |
| 46. |
Stack memory is used |
| A. | to provide additional memory to the base memory |
| B. | to save return addresses of a subroutine |
| C. | to save the status of the microprocessor |
| D. | none of these |
| Answer» C. to save the status of the microprocessor | |
| 47. |
A microprocessor, on arrival of RESET signal returns, from HALT state to |
| A. | execute |
| B. | fetch |
| C. | interrupt |
| D. | none of these |
| Answer» C. interrupt | |
| 48. |
The frequency of the driving network connected between pin 1 and 2 of a 8085 chip must be |
| A. | twice of the desired clock frequency |
| B. | equal to the desired clock frequency |
| C. | four times the desired clock frequency |
| D. | none of these |
| Answer» B. equal to the desired clock frequency | |
| 49. |
A microprocessor with a 12 bit address bus will be able to access |
| A. | 1 kilobyte of memory |
| B. | 4 kilobytes of memory |
| C. | 8 kilobytes of memory |
| D. | 0.4 kilobytes of memory |
| Answer» B. 4 kilobytes of memory | |