When using a sequential code to design a combinational logic in VHDL, if a complete truth table is not defined, the synthesis tool will implement a _______ which is not required.

When using a sequential code to design a combinational logic in VHDL,

1.	When using a sequential code to design a combinational logic in VHDL, if a complete truth table is not defined, the synthesis tool will implement a _______ which is not required.
A.	Clock buffer
B.	Buffer
C.	Flip Flop
D.	Latch
Answer» B. Buffer