The input at the 1, 2, 4, 8 inputs to a 4-line to 16-line decoder with active- low outputs is 1110. As a result, output line 7 is driven LOW.

The input at the 1, 2, 4, 8 inputs to a 4-line to 16-line decoder wit

1.	The input at the 1, 2, 4, 8 inputs to a 4-line to 16-line decoder with active- low outputs is 1110. As a result, output line 7 is driven LOW.
A.	true
B.	false
C.	none of the above
D.	can not predict
Answer» C. none of the above

Discussion

No Comment Found

Related MCQs

Consider the representation of six-bit numbers by two s complement, one scomplement, or by sign and magnitude: In which representation is there overflow fromthe addition of the integers 011000 and 011000?
Indicate which of the following three binary additions are correct? 1.1011 + 1010 = 10101II. 1010 + 1101 = 10111III. 1010 + 1101 = 11111
Minimise the logic function (POS Form) F A,B,C,D) = PI M (1, 2, 3, 8, 9, 10, 11,14) d (7, 15)
If the region beneath the gate is left initially uncharged the gate field must induce achannel before current can flow. Thus the gate voltage enhances thechannel current and sucha device is said to operate in the
THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUTMULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT GATE
Consider an up/down counter that counts between 0 and 15, if external input(X) is 0 the counter counts upward (0000 to 1111) and if external input (X) is 1 the counter counts downward (1111 to 0000), now suppose that the present state is 1100 and X=1, the next state of the counter will be
In the following question, match each of the items A, B and C on the left with an approximation item on the rightA. Shift register can be used 1. for code conversionB. A multiplexer can be used 2. to generate memory slipto selectC. A decoder can be used 3. for parallel to serial conversion4. as many to one switch5. for analog to digital conversion
occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay
A 8-bit serial in / parallel out shift register contains the value 8 , clock signal(s) will be required to shift the value completely out of the register.
In Q output of the last flip-flop of the shift register is connected to the data input of the firstflip-flop of the shift register.

The input at the 1, 2, 4, 8 inputs to a 4-line to 16-line decoder with active- low outputs is 1110. As a result, output line 7 is driven LOW.

Discussion

No Comment Found

Related MCQs

Reply to Comment