The block diagram of a frequency synthesizer consisting of a Phase Locked Loop (PLL) and a divide-by-

20 kHz, 40 kHz, 80 kHz, 160 kHz

160 kHz, 80 kHz, 40 kHz, 20 kHz

The block diagram of a frequency synthesizer consisting of a Phase Loc

1.	The block diagram of a frequency synthesizer consisting of a Phase Locked Loop (PLL) and a divide-by-
A.	10 kHz, 20 kHz, 40 kHz, 80 kHz
B.	20 kHz, 40 kHz, 80 kHz, 160 kHz
C.	80 kHz, 40 kHz, 20 kHz, 10 kHz
D.	160 kHz, 80 kHz, 40 kHz, 20 kHz
Answer» B. 20 kHz, 40 kHz, 80 kHz, 160 kHz