The gates in this figure are implemented using TTL logic. If the input – McqOptions

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1.	The gates in this figure are implemented using TTL logic. If the input of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.
A.	a steady LOW
B.	a steady HIGH
C.	an undefined level
D.	pulses
Answer» B. a steady HIGH

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