Assume a 4-bit parallel in/serial out shift register is loaded with a binary number. How many clock pulses are required after the parallel load has occurred before the first bit in the sequence appears on the serial output line?

Assume a 4-bit parallel in/serial out shift register is loaded with a

1.	Assume a 4-bit parallel in/serial out shift register is loaded with a binary number. How many clock pulses are required after the parallel load has occurred before the first bit in the sequence appears on the serial output line?
A.	0
B.	1
C.	2
D.	3
Answer» C. 2