In VHDL, each instance of a component is given a name followed by a ________ and the name of the library primitive.

In VHDL, each instance of a component is given a name followed by a __

1.	In VHDL, each instance of a component is given a name followed by a ________ and the name of the library primitive.
A.	function
B.	signal
C.	semicolon
D.	colon
Answer» E.