MCQOPTIONS
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MCQOPTIONS
This section includes 10 Mcqs, each offering curated multiple-choice questions to sharpen your Microprocessors knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
The registers that are not available for programmers are |
| A. | data and address registers |
| B. | instruction pointers |
| C. | segment descriptor registers |
| D. | flag registers |
| Answer» D. flag registers | |
| 2. |
The flag bits that indicate the privilege level of current IO operations are |
| A. | Virtual mode flag bits |
| B. | IOPL flag bits |
| C. | Resume flag bits |
| D. | None of the mentioned |
| Answer» C. Resume flag bits | |
| 3. |
The register DR6 hold |
| A. | break point status |
| B. | break point control information |
| C. | break point status and break point control information |
| D. | none of the mentioned |
| Answer» B. break point control information | |
| 4. |
The registers that are used to store four program controllable break point addresses are |
| A. | DR5-DR7 |
| B. | DR0-DR1 |
| C. | DR6-DR7 |
| D. | DR0-DR3 |
| Answer» E. | |
| 5. |
Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are |
| A. | DR0, DR1, DR2 |
| B. | DR4, DR5 |
| C. | DR1, DR4 |
| D. | DR5, DR6, DR7 |
| Answer» C. DR1, DR4 | |
| 6. |
The test register(s) that is provided by 80386 for page caching is |
| A. | test control registers |
| B. | page cache registers |
| C. | test control and test status registers |
| D. | test control and page cache registers |
| Answer» D. test control and page cache registers | |
| 7. |
Which of the following is a system segment register? |
| A. | GDTR |
| B. | LDTR |
| C. | IDTR |
| D. | None of the mentioned |
| Answer» C. IDTR | |
| 8. |
The registers that are together, known as system address registers are |
| A. | GDTR and IDTR |
| B. | IDTR and LDTR |
| C. | TR and GDTR |
| D. | LDTR and TR |
| Answer» B. IDTR and LDTR | |
| 9. |
The descriptor table that the 80386 supports is |
| A. | GDT (Global descriptor table) |
| B. | IDT (Interrupt descriptor table) |
| C. | LDT (Local descriptor table) |
| D. | All of the mentioned |
| Answer» E. | |
| 10. |
The 32-bit control register, that is used to hold global machine status, independent of the executed task is |
| A. | CR0 |
| B. | CR2 |
| C. | CR3 |
| D. | All of the mentioned |
| Answer» E. | |