MCQOPTIONS
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MCQOPTIONS
This section includes 10 Mcqs, each offering curated multiple-choice questions to sharpen your Microprocessors knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
THE_REGISTER_THAT_CAN_BE_AUTOMATICALLY_INCREMENTED_OR_DECREMENTED,_AFTER_EACH_DMA_TRANSFER_IS?$ |
| A. | mask register |
| B. | mode register |
| C. | command register |
| D. | current address register |
| Answer» E. | |
| 2. |
Which_of_the_following_is_a_type_of_DMA_transfer?$ |
| A. | memory read |
| B. | memory write |
| C. | verify transfer |
| D. | all of the mentioned |
| Answer» E. | |
| 3. |
The register that maintains an original copy of the respective initial current address register and current word register i? |
| A. | mode register |
| B. | base address register |
| C. | command register |
| D. | mask register |
| Answer» C. command register | |
| 4. |
Which of these register’s contents is used for auto-initialization (internally)?$ |
| A. | current word register |
| B. | current address register |
| C. | base address register |
| D. | command register |
| Answer» D. command register | |
| 5. |
The current address register is programmed by the CPU as |
| A. | bit-wise |
| B. | byte-wise |
| C. | bit-wise and byte-wise |
| D. | none of the mentioned |
| Answer» C. bit-wise and byte-wise | |
| 6. |
When the count becomes zero in the current word register then |
| A. | Input signal is enabled |
| B. | Output signal is enabled |
| C. | EOP (end of process) is generated |
| D. | Start of process is generated |
| Answer» D. Start of process is generated | |
| 7. |
The register that holds the data byte transfers to be carried out is |
| A. | current word register |
| B. | current address register |
| C. | base address register |
| D. | command register |
| Answer» B. current address register | |
| 8. |
The register that holds the current memory address is |
| A. | current word register |
| B. | current address register |
| C. | base address register |
| D. | command register |
| Answer» C. base address register | |
| 9. |
The priority between the DMA channels requesting the services can be resolved by |
| A. | timing and control block |
| B. | program command control block |
| C. | priority block |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 10. |
The block of 8237 that decodes the various commands given to the 8237 by the CPU is |
| A. | timing and control block |
| B. | program command control block |
| C. | priority block |
| D. | none of the mentioned |
| Answer» C. priority block | |