MCQOPTIONS
Saved Bookmarks
MCQOPTIONS
This section includes 10 Mcqs, each offering curated multiple-choice questions to sharpen your Microprocessors knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
After reset, the stack pointer(SP) is initialized to the address of |
| A. | internal ROM |
| B. | internal RAM |
| C. | external ROM |
| D. | external RAM |
| Answer» C. external ROM | |
| 2. |
The 8051 stack is |
| A. | auto-decrement during PUSH operations |
| B. | auto-increment during POP operations |
| C. | auto-decrement during POP operations |
| D. | auto-increment during PUSH operations |
| Answer» E. | |
| 3. |
The step involved in POP operation is |
| A. | decrement stack by 2 and store 8-bit content to address pointed to by SP |
| B. | store 16-bit content to address pointed to by SP and decrement stack by 1 |
| C. | decrement stack by 1 and store content of top of stack to address pointed to by SP |
| D. | store content of top of stack to address pointed to by SP and then decrement stack by 1 |
| Answer» E. | |
| 4. |
The step involved in PUSH operation is |
| A. | increment stack by 2 and store 8-bit content to address pointed to by SP |
| B. | decrement stack by 1 and store 16-bit content to address pointed to by SP |
| C. | increment stack by 1 and store 8-bit content to address pointed to by SP |
| D. | store 8-bit content to address pointed to by SP and then increment stack by 1 |
| Answer» D. store 8-bit content to address pointed to by SP and then increment stack by 1 | |
| 5. |
The number of bytes stored on the stack during one operation of PUSH or POP is |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» B. 2 | |
| 6. |
All the interrupts are enabled using a special function register called |
| A. | interrupt priority register |
| B. | interrupt register |
| C. | interrupt function register |
| D. | interrupt enable register |
| Answer» E. | |
| 7. |
Among the five interrupts generated by 8051, the highest priority is given to the interrupt |
| A. | IE0 |
| B. | TF1 |
| C. | TF0 |
| D. | IE1 |
| Answer» B. TF1 | |
| 8. |
Among the five interrupts generated by 8051, the lowest priority is given to the interrupt |
| A. | IE0 |
| B. | TF1 |
| C. | TF0 |
| D. | RI |
| Answer» E. | |
| 9. |
The external interrupt that has the lowest priority among the following is |
| A. | TF0 |
| B. | TF1 |
| C. | IE1 |
| D. | NONE |
| Answer» D. NONE | |
| 10. |
The timer generates an interrupt, if the count value reaches to |
| A. | 00FFH |
| B. | FF00H |
| C. | 0FFFH |
| D. | FFFFH |
| Answer» E. | |