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This section includes 7 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Circuits knowledge and support exam preparation. Choose a topic below to get started.
1. |
The output of latches will remain in set/reset untill ___________ |
A. | The trigger pulse is given to change the state |
B. | Any pulse given to go into previous state |
C. | They don t get any pulse more |
D. | The pulse is edge-triggered |
Answer» B. Any pulse given to go into previous state | |
2. |
In S-R flip-flop, if Q = 0 the output is said to be ___________ |
A. | Set |
B. | Reset |
C. | Previous state |
D. | Current state |
Answer» C. Previous state | |
3. |
The basic latch consists of ___________ |
A. | Two inverters |
B. | Two comparators |
C. | Two amplifiers |
D. | Two adders |
Answer» B. Two comparators | |
4. |
The sequential circuit is also called ___________ |
A. | Flip-flop |
B. | Latch |
C. | Strobe |
D. | Adder |
Answer» C. Strobe | |
5. |
The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called ________________ |
A. | Combinational circuits |
B. | Sequential circuits |
C. | Latches |
D. | Flip-flops |
Answer» C. Latches | |
6. |
When both inputs of a J-K flip-flop cycle, the output will ___________ |
A. | Be invalid |
B. | Change |
C. | Not change |
D. | Toggle |
Answer» D. Toggle | |
7. |
One example of the use of an S-R flip-flop is as ___________ |
A. | Transition pulse generator |
B. | Racer |
C. | Switch debouncer |
D. | Astable oscillator |
Answer» D. Astable oscillator | |