MCQOPTIONS
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MCQOPTIONS
This section includes 18 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Circuits knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Assume a 4-bit ripple counter has a failure in the second flip-flop such that it “locks up”. The third and fourth stages will __________ |
| A. | Continue to count with correct outputs |
| B. | Continue to count but have incorrect outputs |
| C. | Stop counting |
| D. | Turn into molten silicon |
| Answer» D. Turn into molten silicon | |
| 2. |
A glitch that appears on the decoded output of a ripple counter is often difficult to see on an oscilloscope because of __________ |
| A. | It is a random event |
| B. | It occurs less frequently than the normal decoded output |
| C. | It is very fast |
| D. | All of the Mentioned |
| Answer» E. | |
| 3. |
A reliable method for eliminating decoder spikes is the technique called ________ |
| A. | Strobing |
| B. | Feeding |
| C. | Wagging |
| D. | Waving |
| Answer» B. Feeding | |
| 4. |
As the number of flip flops are increased, the total propagation delay of __________ |
| A. | Ripple counter increases but that of synchronous counter remains the same |
| B. | Both ripple and synchronous counters increase |
| C. | Both ripple and synchronous counters remain the same |
| D. | Ripple counter remains the same but that of synchronous counter increases |
| Answer» B. Both ripple and synchronous counters increase | |
| 5. |
A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each flip-flop is 50 nsec, the maximum clock frequency that can be used is equal to __________ |
| A. | 20 MHz |
| B. | 10 MHz |
| C. | 5 MHz |
| D. | 4 MHz |
| Answer» D. 4 MHz | |
| 6. |
The main drawback of a ripple counter is that __________ |
| A. | It has a cumulative settling time |
| B. | It has a distributive settling time |
| C. | It has a productive settling time |
| D. | It has an associative settling time |
| Answer» B. It has a distributive settling time | |
| 7. |
What is the maximum delay that can occur if four flip-flops are connected as a ripple counter and each flip-flop has propagation delays of tPHL = 22 ns and tPLH = 15 ns? |
| A. | 15 ns |
| B. | 22 ns |
| C. | 60 ns |
| D. | 88 ns |
| Answer» E. | |
| 8. |
A ripple counter’s speed is limited by the propagation delay of __________ |
| A. | Each flip-flop |
| B. | All flip-flops and gates |
| C. | The flip-flops only with gates |
| D. | Only circuit gates |
| Answer» B. All flip-flops and gates | |
| 9. |
A ripple counter’s speed is limited by the propagation delay of ____________ |
| A. | Each flip-flop |
| B. | All flip-flops and gates |
| C. | The flip-flops only with gates |
| D. | Only circuit gates |
| Answer» B. All flip-flops and gates | |
| 10. |
A_RELIABLE_METHOD_FOR_ELIMINATING_DECODER_SPIKES_IS_THE_TECHNIQUE_CALLED_________?$ |
| A. | Strobing |
| B. | Feeding |
| C. | Wagging |
| D. | Waving |
| Answer» B. Feeding | |
| 11. |
Assume a 4-bit ripple counter has a failure in the second flip-flop such that it “locks up”. The third and fourth stages will$# |
| A. | Continue to count with correct outputs |
| B. | Continue to count but have incorrect outputs |
| C. | Stop counting |
| D. | Turn into molten silicon |
| Answer» D. Turn into molten silicon | |
| 12. |
A_glitch_that_appears_on_the_decoded_output_of_a_ripple_counter_is_often_difficult_to_see_on_an_oscilloscope_because$ |
| A. | It is a random event |
| B. | It occurs less frequently than the normal decoded output |
| C. | It is very fast |
| D. | All of the Mentioned |
| Answer» E. | |
| 13. |
As the number of flip flops are increased, the total propagation delay o? |
| A. | Ripple counter increases but that of synchronous counter remains the same |
| B. | Both ripple and synchronous counters increase |
| C. | Both ripple and synchronous counters remain the same |
| D. | Ripple counter remains the same but that of synchronous counter increases |
| Answer» B. Both ripple and synchronous counters increase | |
| 14. |
A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each flip-flop is 50 nsec, the maximum clock frequency that can be used is equal to |
| A. | 20 MHz |
| B. | 10 MHz |
| C. | 5 MHz |
| D. | 4 MHz |
| Answer» D. 4 MHz | |
| 15. |
The main drawback of a ripple counter is that |
| A. | It has a cumulative settling time |
| B. | It has a distributive settling time |
| C. | It has a productive settling time |
| D. | None of the Mentioned |
| Answer» B. It has a distributive settling time | |
| 16. |
A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________ |
| A. | 15 ns |
| B. | 30 ns |
| C. | 45 ns |
| D. | 60 ns |
| Answer» E. | |
| 17. |
A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________ |
| A. | 12 ms |
| B. | 24 ns |
| C. | 48 ns |
| D. | 60 ns |
| Answer» E. | |
| 18. |
A ripple counter’s speed is limited by the propagation delay of: |
| A. | Each flip-flop |
| B. | All flip-flops and gates |
| C. | The flip-flops only with gates |
| D. | Only circuit gates |
| Answer» B. All flip-flops and gates | |