MCQOPTIONS
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MCQOPTIONS
This section includes 202 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science knowledge and support exam preparation. Choose a topic below to get started.
| 151. |
A basic instruction that can be interpreted by a compuer generally has |
| A. | an operand and an address |
| B. | a decoder and an accumulator |
| C. | sequence register and decoder |
| D. | an address and decoder |
| Answer» B. a decoder and an accumulator | |
| 152. |
Both the arithmetic logic unit (ALU) and control section of CPU employ special purpose storage locations called |
| A. | decoders |
| B. | buffers |
| C. | multiplexer |
| D. | registers |
| Answer» E. | |
| 153. |
To put the microprocessor in the wait state |
| A. | lower the HOLD input |
| B. | lower the READY input |
| C. | raise the HOLD input |
| D. | raise the READY input |
| Answer» C. raise the HOLD input | |
| 154. |
A stack is a/an |
| A. | 8-bit register in the microprocessor |
| B. | 16-bit register in the microprocessor |
| C. | set of memory locations in R/w memory reserved for storing information temporarily during the execution of a program |
| D. | 16-bit memory address stored in the h program counter |
| Answer» D. 16-bit memory address stored in the h program counter | |
| 155. |
The address range to which I/O chip will respond is |
| A. | 000H to FFFF H |
| B. | 0000 H to 5FFF H |
| C. | 4000 H to 5FFFF H |
| D. | 3000 H to FFFF H |
| Answer» C. 4000 H to 5FFFF H | |
| 156. |
The memory adress range to which RAM will respond |
| A. | 0000 H to 1 FFF H |
| B. | 0000 H to 5FFF H |
| C. | 4000 H to 5FFFF H |
| D. | 3000H to FFFF H |
| Answer» C. 4000 H to 5FFFF H | |
| 157. |
Which of the following interrupts are unmaskable interrupts? |
| A. | RST 5.5 |
| B. | RST 7.5 |
| C. | TRAP |
| D. | INTR1 |
| Answer» D. INTR1 | |
| 158. |
Serial input data of 8085 can be loaded into bit7 of the accumulator by |
| A. | executing a RIM instruction |
| B. | execution RST 1 |
| C. | using TRAP |
| D. | none of these |
| Answer» B. execution RST 1 | |
| 159. |
When the HLT instruction of a 8085 micro processor is executed, the microprocessor |
| A. | is disconnected from the system bus till the reset is pressed |
| B. | halts execution of the program and returns to monitor |
| C. | enters into a halt state and the buses are tri-stated |
| D. | reloads the program from the location 0024 and 0025 H. |
| Answer» D. reloads the program from the location 0024 and 0025 H. | |
| 160. |
When a program is being executed in an 8085 microprocessor, its profram Counter contains |
| A. | number of instructions in the Current Program that have already been executed |
| B. | the total number of instructions in the program being executed |
| C. | memory address of the instruction that is being currently executed |
| D. | memory address of the instruction that is to be executed next |
| Answer» E. | |
| 161. |
In a microcomputer, WAIT states are used to |
| A. | make the processor wait during a DMA operation |
| B. | make the processor wait during a power interrupt processing |
| C. | make the processor wait during a power shutdown |
| D. | interface slow peripherals to the processor |
| Answer» E. | |
| 162. |
The CPU of a computer takes instructions from the memory and executes them. This process is called |
| A. | load cycle |
| B. | time sequence |
| C. | fetch-execute cycle |
| D. | clock cycle |
| Answer» D. clock cycle | |
| 163. |
The Process of fetching and exacuting instructions. pne at a time, in order of increasing address is called |
| A. | instruction execution |
| B. | straight line sequencing |
| C. | instruction fetch |
| D. | random sequencing |
| Answer» C. instruction fetch | |
| 164. |
The addressing mode used in the instruction PUSH B is |
| A. | direct |
| B. | register |
| C. | register indirect |
| D. | immediate |
| Answer» D. immediate | |
| 165. |
The number of instructions needed to add 'n' numbers and store the result in memory using only one instructions is |
| A. | n |
| B. | n=1 |
| C. | n-1 |
| D. | independent of n |
| Answer» C. n-1 | |
| 166. |
Pseudo - instructions are |
| A. | assembler directives |
| B. | instructions in any program that have no corresponding machine code instruction |
| C. | instruction in any program whose presence or absence will not change the output for any input |
| D. | none of these |
| Answer» B. instructions in any program that have no corresponding machine code instruction | |
| 167. |
The TRAP interrupt mechanism of the 8085 microposser executs |
| A. | an RST by hardware |
| B. | the instruction supplied by external device through the INTA signal |
| C. | an instruction from memory location 20 H |
| D. | a NOP |
| Answer» B. the instruction supplied by external device through the INTA signal | |
| 168. |
The programmable interval times is |
| A. | 8251 |
| B. | 8250 |
| C. | 8253 |
| D. | 8275 |
| Answer» D. 8275 | |
| 169. |
The program Counter (PC) |
| A. | is a register |
| B. | during exacution of the current instruction, its content changes |
| C. | both (a) and (b) |
| D. | none of these |
| Answer» D. none of these | |
| 170. |
When a subroutine is called, then address of the instruction fiollowing the CAL instruction is stored in/on the. |
| A. | stack pointer |
| B. | Accumulator |
| C. | program counter |
| D. | Stack |
| Answer» D. Stack | |
| 171. |
The Capacity of program counter (PC) is |
| A. | 8 bits |
| B. | 12 bits |
| C. | 16 bits |
| D. | 32 bits |
| Answer» C. 16 bits | |
| 172. |
Which of the following is not typically found in the status register of a micro processor? |
| A. | Overflow |
| B. | Zero result |
| C. | Negative result |
| D. | None of the above |
| Answer» E. | |
| 173. |
In the absolute addressing mode |
| A. | operand is inside the instruction |
| B. | address of the operand is inside the instruction |
| C. | register containing the address of the operand is specified inside theinstruction |
| D. | location of the operand is implicit. |
| Answer» E. | |
| 174. |
CPU has two modes-privileged and non privileged In order to change the mode from privileged to non-privileged |
| A. | a hardware interrupt is needed |
| B. | a Software interrupt is needed |
| C. | a privileged instruction is needed |
| D. | a non - privileged instruction (which does not generate an interrupt) is needed |
| Answer» E. | |
| 175. |
If a Processor does not have any stack pointer register, then |
| A. | it cannot have subroutine call instruction |
| B. | it Can have subroutine call instruction, but no nested subroutine calls |
| C. | nested subroutine calls are possible, but interrupts are not |
| D. | all sequences of subroutine calls and also interrupts are possible |
| Answer» E. | |
| 176. |
Which of the following need not necessarily be saved on a Context switch between process? |
| A. | General purpose registers |
| B. | Translation lookside buffer |
| C. | program counter |
| D. | All of these |
| Answer» C. program counter | |
| 177. |
The 8085 microprocessor responds to the presence of an interrupt |
| A. | AS SOON AS the TRAP pin becomes high |
| B. | by checking the TRAP pin for high status at the end of each instruction fetch |
| C. | by checking the TRAP pin for high status at the end of the execution of each instruction |
| D. | by checking the TRAP pin for high status at regular intervals |
| Answer» D. by checking the TRAP pin for high status at regular intervals | |
| 178. |
A Certain processor supports only the immidiate and the direct addressing modes. Which of the follwing programming language features cannot be implemented on this processor? |
| A. | Pointers |
| B. | Arrays |
| C. | Records |
| D. | All of these |
| Answer» E. | |
| 179. |
In a multiprocesscr configuration tow co -processos are connected to the host 8086 processor the tow co-processor instruction sets |
| A. | must be the same |
| B. | may overlap |
| C. | must be disjont |
| D. | must be the sane as that of the host |
| Answer» E. | |
| 180. |
If we use 3 bits in the instruction word to indicate if an index register is to be used then the number of index registers to be used in the machyine will be |
| A. | 3 |
| B. | 6 |
| C. | 7 |
| D. | 8 |
| Answer» B. 6 | |
| 181. |
Micro program is |
| A. | the name of source program in micro computers |
| B. | the set of instructions indicating the primitive operations in a system |
| C. | primitive form of macros used in assembly language programming |
| D. | program of very small size |
| Answer» C. primitive form of macros used in assembly language programming | |
| 182. |
The stack pointer in the microprocessor is a |
| A. | 16 bit register thet point to stack memory locations |
| B. | 16 bit accumulator |
| C. | memory location in the stack |
| D. | flag register used for the stack |
| Answer» B. 16 bit accumulator | |
| 183. |
In a generic microprocessor instruction cycle time is |
| A. | shorter than machine cycle time |
| B. | larger than machine cycle time |
| C. | exactly double the machine cycle time |
| D. | exactly the same as the machine cycle time |
| Answer» E. | |
| 184. |
Microprocessor 8085 is the enhanced version of with essentially the same construction set |
| A. | 6800 |
| B. | 68000 |
| C. | 8080 |
| D. | 8000 |
| Answer» D. 8000 | |
| 185. |
An instruction used to set the carry flag in a computer can be classified as |
| A. | data transfer |
| B. | process control |
| C. | logical |
| D. | program control |
| Answer» C. logical | |
| 186. |
In a microprocessor system the RST instruction well cause an interrupt |
| A. | only if an interrupt service routine is not being executed |
| B. | only if a bit in the interrupt mask is made 0 |
| C. | only if interrupts have been enabled by an EI instruction |
| D. | none of these |
| Answer» D. none of these | |
| 187. |
Number of machine cycles required for RET instruction in 8085 microprocessor is |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 5 |
| Answer» D. 5 | |
| 188. |
The ability to temporararily halt the CPU and use this time to send information on buses is called |
| A. | direct memory access |
| B. | vectoring the interrut |
| C. | polling |
| D. | cycle stealing |
| Answer» E. | |
| 189. |
An interrupt can be temporarily ignored by the counter is called |
| A. | vectored interrupt |
| B. | non -maskable interrupt |
| C. | maskable interrupt |
| D. | low priority interrupt |
| Answer» C. maskable interrupt | |
| 190. |
Which of the following register is used in the control unit of the CPUt to indicate the next instruction which is to be executed |
| A. | Accumulator |
| B. | Index register |
| C. | Instruction |
| D. | program counter |
| Answer» E. | |
| 191. |
Which of the following is set of general purpose internal registers |
| A. | stack |
| B. | scratch pad |
| C. | address register |
| D. | status register |
| Answer» C. address register | |
| 192. |
The devine which is used to connect a peripheral to bus is called |
| A. | control register |
| B. | interface |
| C. | communicatication protocol |
| D. | none of these |
| Answer» C. communicatication protocol | |
| 193. |
Which of the following information holds the information before going to the decoder |
| A. | control register |
| B. | data register |
| C. | Accumulator |
| D. | address register |
| Answer» C. Accumulator | |
| 194. |
The register used as a working area in CPU is |
| A. | program counter |
| B. | instruction register |
| C. | instruction decoder |
| D. | accumulator |
| Answer» E. | |
| 195. |
Which of the following is used as stor age locationns both in the ALU and the control section of a computer |
| A. | Accumulator |
| B. | Register |
| C. | Adder |
| D. | Decoder |
| Answer» C. Adder | |
| 196. |
The register which contains the data to be written into or read out of the data to be written intu or read out of the addressed location is called |
| A. | memory address register |
| B. | memory data register |
| C. | program computer |
| D. | index register |
| Answer» C. program computer | |
| 197. |
The register which keeps trcck of the execution of a program and which contains the memory address of the in struction currently being executed is called |
| A. | index register |
| B. | memory address register |
| C. | program counter |
| D. | instruction register |
| Answer» D. instruction register | |
| 198. |
Which of the following is responsible for coordinating various operatings using timing signals |
| A. | ALU |
| B. | control unit |
| C. | memory unit |
| D. | I/O unit |
| Answer» C. memory unit | |
| 199. |
In a microprocessor system with memory mapped I/O |
| A. | devices have 8 -bit addresses |
| B. | devices are accessed using In and OUT instructions |
| C. | there can be a maximum of 256 input devices and 256 output devices |
| D. | arithmetic and logic operations can be directly performed with the I/O data |
| Answer» E. | |
| 200. |
A basic instruction that can be interpreted by a computer generally has |
| A. | an operand and an address |
| B. | a decoder and an accumulator |
| C. | sequence register and decoder |
| D. | an address and decoder |
| Answer» B. a decoder and an accumulator | |