MCQOPTIONS
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MCQOPTIONS
This section includes 17 Mcqs, each offering curated multiple-choice questions to sharpen your Java knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Match List I with List IIList IList II(A) Handshaking(I) I/O interface informs the CPU that device is ready for transfer(B) Programmed I/O(II) requires two control signals working in opposite directions(C) Interrupt-initiated I/O(III) has local memory & control large set of I/O devices.(D) I/O processor(IV) require CPU to check the I/O flag & perform transfer Choose the correct answer from the options given below: |
| A. | A - I, B - II, C - 10, D - IV |
| B. | A - II, B - IV, C - III, D - I |
| C. | A - II, B - IV, C - I, D - III |
| D. | A - IV, B - III, C - II, D - I |
| Answer» D. A - IV, B - III, C - II, D - I | |
| 2. |
Arrange the following addresses in ascending order of their priorityA. Address for divide error is 0000HB. Address for one - byte interrupt instruction, INT is 000CHC. Address for overflow, INTO instruction is 0010HD. Address for single step trap - TF must be set is 0004HE. Address for non maskable interrupt is 0008HChoose the correct answer from the options given below: |
| A. | A, D, E, B, C |
| B. | A, E, D, B, C |
| C. | A, E, B, C, D |
| D. | A, D, B, E, C |
| Answer» B. A, E, D, B, C | |
| 3. |
On which one of the following output devices is hard to copy often displayed? |
| A. | Monitor |
| B. | Scanner |
| C. | Printer |
| D. | Key Board |
| Answer» D. Key Board | |
| 4. |
An interface that provides I/o transfer of data directly to and from the memory unit and the peripheral is termed as _____ |
| A. | DDA |
| B. | Serial Interface |
| C. | BR |
| D. | DMA |
| Answer» E. | |
| 5. |
During DMA transfer, DMA controller transfers data ______. |
| A. | directly between memory and registers |
| B. | directly between the I/O module and main memory |
| C. | directly from memory to CPU |
| D. | directly from CPU to Memory |
| Answer» C. directly from memory to CPU | |
| 6. |
Hardware mechanism that enables a device to notify the CPU is called: |
| A. | Busy-waiting |
| B. | Interrupt |
| C. | Polling |
| D. | DMA |
| Answer» C. Polling | |
| 7. |
Consider the following statements:Arithmetic Logic Unit (ALU)1. Performs arithmetic operations2. Performs comparisons.3. Communicates with I/O devices4. Keeps watch on the systemWhich of these statements are correct? |
| A. | 1 Only |
| B. | 1 and 2 only |
| C. | 2 and 3 |
| D. | 1 and 4 |
| Answer» C. 2 and 3 | |
| 8. |
For long distance communication which of the following data transfer technique is used? |
| A. | Serial Transfer |
| B. | Parallel Transfer |
| C. | Serial Parallel transfer |
| D. | Parallel Serial Transfer |
| Answer» B. Parallel Transfer | |
| 9. |
A computer has only one processor which is known as: |
| A. | Uniprocessor |
| B. | Multiprocessor |
| C. | Multithreaded |
| D. | Multi-meter |
| Answer» B. Multiprocessor | |
| 10. |
In 8086, example for non maskable interrupts is: |
| A. | TRAP |
| B. | RST 6.5 |
| C. | INTR |
| D. | RST 6.6 |
| Answer» B. RST 6.5 | |
| 11. |
Chain printer is a _______ printer. |
| A. | non-impact |
| B. | daisy wheel |
| C. | dot matrix |
| D. | line |
| Answer» E. | |
| 12. |
Consider the following statements.I. Daisy chaining is used to assign priorities in attending interrupts.II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.III. In polling, the CPU periodically checks the status bits to know if any device needs its attention.IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.Which of the above statements is/are TRUE? |
| A. | I and II only |
| B. | I and IV only |
| C. | I and III only |
| D. | III only |
| Answer» D. III only | |
| 13. |
Consider the following processor design characteristics.I. Register-to-register arithmetic operations onlyII. Fixed-length instruction formatIII. Hardwired control unitWhich of the characteristics above are used in the design of a RISC processor? |
| A. | I and II only |
| B. | II and III only |
| C. | I and III only |
| D. | I, II and III |
| Answer» E. | |
| 14. |
Direction: Given question consists of two statements, one labeled as the 'Assertion (A)' and the other as 'Reason (R)'. You are to examine these two statements carefully and select the answers to these items using the codes given below.Assertion (A): The low-level control of an I / O device is easier at the hardware level.Reason (R): It requires managing a set of concurrent events. |
| A. | Both A and R are individually true and R is the correct explanation of A |
| B. | Both A and R are individually true but R is NOT the correct explanation of A |
| C. | A is true but R is false |
| D. | A is false but R is true |
| Answer» E. | |
| 15. |
Advantage of synchronous sequential circuits over asynchronous one is |
| A. | Lower hardware requirement |
| B. | Better noise immunity |
| C. | Faster operation |
| D. | None of the above |
| Answer» E. | |
| 16. |
Which of these is a Basic interface that all other interface inherits? |
| A. | Set |
| B. | Array |
| C. | List |
| D. | Collection |
| Answer» E. | |
| 17. |
Which of this interface must contain a unique element? |
| A. | Set |
| B. | List |
| C. | Array |
| D. | Collection |
| Answer» B. List | |