MCQOPTIONS
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MCQOPTIONS
This section includes 29 Mcqs, each offering curated multiple-choice questions to sharpen your Embedded Systems knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
The transfer between CPU and Cache is ______________ |
| A. | Block transfer |
| B. | Word transfer |
| C. | Set transfer |
| D. | Associative transfer |
| Answer» C. Set transfer | |
| 2. |
The number of sign bits in a 32-bit IEEE format is ____ |
| A. | 1 |
| B. | 11 |
| C. | 9 |
| D. | 23 |
| Answer» B. 11 | |
| 3. |
In ____________ mapping, the data can be mapped anywhere in the Cache Memory. |
| A. | Associative |
| B. | Direct |
| C. | Set Associative |
| D. | Indirect |
| Answer» B. Direct | |
| 4. |
Whenever the data is found in the cache memory it is called as _________ |
| A. | HIT |
| B. | MISS |
| C. | FOUND |
| D. | ERROR |
| Answer» B. MISS | |
| 5. |
How many divisions are possible in the cache memory based on the tag or index address? |
| A. | 3 |
| B. | 2 |
| C. | 4 |
| D. | 5 |
| Answer» D. 5 | |
| 6. |
What are the basic elements required for cache operation? |
| A. | memory array, multivibrator, counter |
| B. | memory array, comparator, counter |
| C. | memory array, trigger circuit, a comparator |
| D. | memory array, comparator, CPU |
| Answer» C. memory array, trigger circuit, a comparator | |
| 7. |
Which factor determines the cache performance? |
| A. | software |
| B. | peripheral |
| C. | input |
| D. | output |
| Answer» B. peripheral | |
| 8. |
WHICH_FACTOR_DETERMINES_THE_CACHE_PERFORMANCE??$ |
| A. | software |
| B. | peripheral |
| C. | input |
| D. | output |
| Answer» B. peripheral | |
| 9. |
THE_NUMBER_OF_SIGN_BITS_IN_A_32-BIT_IEEE_FORMAT_IS_____?$ |
| A. | 1 |
| B. | 11 |
| C. | 9 |
| D. | 23 |
| Answer» B. 11 | |
| 10. |
How many divisions are possible in the cache memory based on the tag or index address?$ |
| A. | 3 |
| B. | 2 |
| C. | 4 |
| D. | 5 |
| Answer» D. 5 | |
| 11. |
What are the basic elements required for cache operation?$ |
| A. | memory array, multivibrator, counter |
| B. | memory array, comparator, counter |
| C. | memory array, trigger circuit, a comparator |
| D. | memory array, comparator, CPU |
| Answer» C. memory array, trigger circuit, a comparator | |
| 12. |
The_transfer_between_CPU_and_Cache_is_______________$ |
| A. | Block transfer |
| B. | Word transfer |
| C. | Set transfer |
| D. | Associative transfer |
| Answer» C. Set transfer | |
| 13. |
What is the full form of DMA in Cache Memory? |
| A. | direct memory access |
| B. | direct main access |
| C. | data main access |
| D. | data memory address |
| Answer» B. direct main access | |
| 14. |
Which of the following refers to the number of consecutive bytes which are associated with each cache entry? |
| A. | cache size |
| B. | associative set |
| C. | cache line |
| D. | cache word |
| Answer» D. cache word | |
| 15. |
In ____________ mapping, the data can be mapped anywhere in the Cache Memory? |
| A. | Associative |
| B. | Direct |
| C. | Set Associative |
| D. | Indirect |
| Answer» B. Direct | |
| 16. |
Which of the following allows speculative execution? |
| A. | 12-way set associative cache |
| B. | 8-way set associative cache |
| C. | direct mapped cache |
| D. | 4-way set associative cache |
| Answer» D. 4-way set associative cache | |
| 17. |
Which of the following is an efficient method of cache updating? |
| A. | Snoopy writes |
| B. | Write through |
| C. | Write within |
| D. | Buffered write |
| Answer» B. Write through | |
| 18. |
How many possibilities of mapping does a direct mapped cache have? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» B. 2 | |
| 19. |
Which of the following is not a write policy to avoid Cache Coherence? |
| A. | Write through |
| B. | Write within |
| C. | Write back |
| D. | Buffered write |
| Answer» C. Write back | |
| 20. |
What is the size of the cache for an 8086 processor? |
| A. | 64 Kb |
| B. | 128 Kb |
| C. | 32 Kb |
| D. | 16 Kb |
| Answer» B. 128 Kb | |
| 21. |
When the data at a location in cache is different from the data located in the main memory, the cache is called _____________ |
| A. | Unique |
| B. | Inconsistent |
| C. | Variable |
| D. | Fault |
| Answer» C. Variable | |
| 22. |
Which factor determines the number of cache entries? |
| A. | set commutativity |
| B. | set associativity |
| C. | size of the cache |
| D. | number of caches |
| Answer» C. size of the cache | |
| 23. |
LRU stands for ___________ |
| A. | Low Rate Usage |
| B. | Least Rate Usage |
| C. | Least Recently Used |
| D. | Low Required Usage |
| Answer» D. Low Required Usage | |
| 24. |
Which of the following is a common cache? |
| A. | DIMM |
| B. | SIMM |
| C. | TLB |
| D. | Cache |
| Answer» D. Cache | |
| 25. |
Whenever the data is found in the cache memory it is called as _________ |
| A. | HIT |
| B. | MISS |
| C. | FOUND |
| D. | ERROR |
| Answer» B. MISS | |
| 26. |
Which of the following determines a high hit rate of the cache memory? |
| A. | size of the cache |
| B. | number of caches |
| C. | size of the RAM |
| D. | cache access |
| Answer» B. number of caches | |
| 27. |
Cache Memory is implemented using the DRAM chips. |
| A. | True |
| B. | False |
| Answer» C. | |
| 28. |
Which factor determines the effectiveness of the cache? |
| A. | hit rate |
| B. | refresh cycle |
| C. | refresh rate |
| D. | refresh time |
| Answer» B. refresh cycle | |
| 29. |
Which of the following is more quickly accessed? |
| A. | RAM |
| B. | Cache memory |
| C. | DRAM |
| D. | SRAM |
| Answer» C. DRAM | |