MCQOPTIONS
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MCQOPTIONS
This section includes 657 Mcqs, each offering curated multiple-choice questions to sharpen your Testing Subject knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
The register which keeps track of the execution of a program and which contains the memory address of the instruction currently being executed is called |
| A. | index register |
| B. | memory address register |
| C. | program counter |
| D. | instruction register |
| Answer» D. instruction register | |
| 2. |
Consider the following set of instructions: STC CMC MOV A,B RAL MOV B,A This set of instructions |
| A. | doubles the number in Register by B |
| B. | divides the number in Register by 2 |
| C. | multiples B by A |
| D. | adds A and B |
| Answer» C. multiples B by A | |
| 3. |
Following program is written for an 8085 microprocessor to add two bytes located at memory addresses 1FFE and 1FFF LXI H, 1FFF MOV B, M INR L MOV A,M ADD B INR L MOV M, A XOR A On completion of the execution of the program, the result of addition is found |
| A. | in the register A |
| B. | at the memory address 1000 |
| C. | at the memory address 1F00 |
| D. | at the memory address 2000 |
| Answer» E. | |
| 4. |
In a 8085 microprocessor, the following sequence of instructions is executed: STC CMC MOVE A,B RAL MOVE B,A After the last instruction, the output will |
| A. | rotate the contents of the accumulator and store it in B |
| B. | get the contents of B register into accumulator and rotate it to left by one bit |
| C. | double contents of B register |
| D. | manipulate carry in A and B |
| Answer» D. manipulate carry in A and B | |
| 5. |
In an 8085 microprocessor, the contents of the Accumulator, after the following instructions are executed will become XRA A MVIB F0H SUB B |
| A. | 01 H |
| B. | 0F |
| C. | F0H |
| D. | 10 H |
| Answer» E. | |
| 6. |
An advantage of memory interfacing is that |
| A. | a larger memory is obtained |
| B. | effective speed of the memory is increased |
| C. | the cost of the memory is reduced |
| D. | a non-volatile memory is obtained |
| Answer» C. the cost of the memory is reduced | |
| 7. |
Return from a subroutine is affected by |
| A. | a jump instruction |
| B. | an RST instruction |
| C. | a RET instruction |
| D. | a hardware interrupt signal |
| Answer» D. a hardware interrupt signal | |
| 8. |
The three buses associated with three-bus system are I/O bus, memory bus and the |
| A. | address bus |
| B. | unibus |
| C. | direct memory access bus |
| D. | data bus |
| Answer» D. data bus | |
| 9. |
Which of the following cycle is required to fetch and execute information? |
| A. | Clock cycle |
| B. | Tri cycle |
| C. | Introduction cycle |
| D. | Memory |
| Answer» D. Memory | |
| 10. |
The register whose contents may be added to or subtracted from the operand address prior to or during the execution of an instruction is known as |
| A. | index register |
| B. | control register |
| C. | address register |
| D. | none of these |
| Answer» B. control register | |
| 11. |
SHIFT LEFT instruction causes all bits shifted from one position to the left with rightmost bit set to zero. The effect is to |
| A. | multiply by 2 |
| B. | divide by 2 |
| C. | SET the most significant bit |
| D. | none of these |
| Answer» B. divide by 2 | |
| 12. |
8085 microprocessor is a |
| A. | zero address microprocessor |
| B. | one address microprocessor |
| C. | two address microprocessor |
| D. | none of these |
| Answer» C. two address microprocessor | |
| 13. |
Setting contents of a register to zero can be efficiently done by |
| A. | Movimmediate instruct ion using zero as immediate data |
| B. | AND immediate instruction using zero as immediate data |
| C. | XORing register with itself |
| D. | none of these |
| Answer» D. none of these | |
| 14. |
Two operands can be checked for equality using |
| A. | OR-operation |
| B. | AND-operation |
| C. | X-OR operation |
| D. | none of these |
| Answer» D. none of these | |
| 15. |
A microprocessor is also referred to as |
| A. | the chip that does some calculations for the computer |
| B. | the computer on a chip |
| C. | the chip that is responsible for data transfer |
| D. | none of these |
| Answer» C. the chip that is responsible for data transfer | |
| 16. |
An interrupt in which the external device supplies its address as well as the interrupt request is known as |
| A. | vectored interrupt |
| B. | maskable interrupt |
| C. | non-maskable interrupt |
| D. | designated interrupt |
| Answer» B. maskable interrupt | |
| 17. |
An interrupt which can be temporarily ignored by the counter is known as |
| A. | vectored interrupt |
| B. | non-maskable interrupt |
| C. | maskable interrupt |
| D. | low priority interrupt |
| Answer» D. low priority interrupt | |
| 18. |
The bus which is used to transfer data from main memory to peripheral device is the |
| A. | data bus |
| B. | input bus |
| C. | DMA bus |
| D. | output bus |
| Answer» D. output bus | |
| 19. |
After completing the execution, microprocessor return to |
| A. | Halt state |
| B. | Fetch state |
| C. | Execute state |
| D. | Interrupt state |
| Answer» C. Execute state | |
| 20. |
The stack pointer in the 8085 microprocessor is a |
| A. | 16 bit register which points to stack memory locations |
| B. | 16 bit accumulator |
| C. | memory location in the stack |
| D. | flag register used for the stack |
| Answer» B. 16 bit accumulator | |
| 21. |
A microprocessor with 12 address lines is capable of addressing |
| A. | 1024 locations |
| B. | 2028 locations |
| C. | 4096 locations |
| D. | 64 K locations |
| Answer» D. 64 K locations | |
| 22. |
The flow and timing of data to and from the microprocessor is regulated by |
| A. | control pins |
| B. | address pins |
| C. | data pins |
| D. | power pins |
| Answer» B. address pins | |
| 23. |
The process of fetching and executing instructions one at a time in the order of increasing addresses is known as |
| A. | instruction execution |
| B. | straight line sequencing |
| C. | instruction fetching |
| D. | random sequencing |
| Answer» C. instruction fetching | |
| 24. |
The register which contains the data to be written into or read out of the addressed location is known as |
| A. | index register |
| B. | memory address register |
| C. | memory data register |
| D. | program counter |
| Answer» D. program counter | |
| 25. |
Which of the following signal is used when a microprocessor wants to address the memory? |
| A. | IO/ M |
| B. | Status signals |
| C. | ALE |
| D. | HOLD and HLDA |
| Answer» D. HOLD and HLDA | |
| 26. |
Program Counter is used to |
| A. | store address of the next instruction to be executed |
| B. | store temporary data to be used in arithmetic operations |
| C. | store the status of the microprocessor |
| D. | none of these |
| Answer» B. store temporary data to be used in arithmetic operations | |
| 27. |
The selection of a microprocessor for an application is done keeping in mind |
| A. | speed compatibility of microprocessor with perip-herals |
| B. | the time critical behaviour of the application |
| C. | the size of program required to implement certain functions |
| D. | all of these |
| Answer» E. | |
| 28. |
In microprocessor architecture, flag indicates |
| A. | the number of microprocessor |
| B. | the name of the manufacturer |
| C. | the inte the bit-size of the micro-processor nal status of the CPU |
| D. | the bit-size of the micro-processor |
| Answer» D. the bit-size of the micro-processor | |
| 29. |
Stack pointer is a register which comes into use |
| A. | whenever a data is read from the memory |
| B. | whenever a data is written into the memory |
| C. | whenever the output variable is sent out of the CPU |
| D. | whenever an interrupt or high priority call comes from external devices |
| Answer» E. | |
| 30. |
A program counter is a storage register for |
| A. | location of data in memory |
| B. | location of instruction in memory |
| C. | binary code for the operation to be performed |
| D. | address of the next instruction to be executed |
| Answer» E. | |
| 31. |
An instruction register is storage for |
| A. | location of data in memory |
| B. | location of instruction in memory |
| C. | binary code for the operation to be performed |
| D. | address of the next instruction to be executed |
| Answer» D. address of the next instruction to be executed | |
| 32. |
The microprocessor contains ROM chip which contains |
| A. | control function |
| B. | arithmetic functions |
| C. | instructions to execute data |
| D. | memory functions |
| Answer» D. memory functions | |
| 33. |
The basic elements of a micro-processor are |
| A. | ALU, memory |
| B. | ALU, control unit |
| C. | ALU, memory, I/O device |
| D. | ALU, control unit, memory |
| Answer» C. ALU, memory, I/O device | |
| 34. |
Address usually is |
| A. | alphabetical |
| B. | numerical |
| C. | alpha-numerical |
| D. | none of these |
| Answer» C. alpha-numerical | |
| 35. |
Accumulation is a device which |
| A. | stores a number |
| B. | adds two numbers |
| C. | adds and stores previously stored number to another number |
| D. | none of these |
| Answer» D. none of these | |
| 36. |
ACK indicates reception of |
| A. | correct data |
| B. | incorrect data |
| C. | insufficient data |
| D. | sufficient data |
| Answer» B. incorrect data | |
| 37. |
A microprocessor is a minimum combination of |
| A. | mP and clock |
| B. | mP, clock and ROMs |
| C. | mP, clock, RAMs and ROMs |
| D. | mP, clock, RAM, ROM, PIA and ACIA |
| Answer» E. | |
| 38. |
Direct Memory Access Channel (DMA) facilitates data to move into and out of the system |
| A. | on first-come first-serve basis |
| B. | with equal time delay |
| C. | without sub routine |
| D. | without programme intervention |
| Answer» C. without sub routine | |
| 39. |
Which of the following actions detect locations, and remove mistakes from a programme routine? |
| A. | Erase |
| B. | Debug |
| C. | Diagnose |
| D. | Emulate |
| Answer» C. Diagnose | |
| 40. |
Mnemonic symbols are used |
| A. | to denote address |
| B. | to employ hamming code |
| C. | to denote error |
| D. | to assist human memory |
| Answer» E. | |
| 41. |
Flag is a character for |
| A. | identification of a word |
| B. | occurance of some condition |
| C. | marking a tagging |
| D. | all of these |
| Answer» E. | |
| 42. |
PSW stands for |
| A. | accumulator contents |
| B. | flag byte |
| C. | accumulator and the flag byte |
| D. | accumulator and temporary register byte |
| Answer» D. accumulator and temporary register byte | |
| 43. |
A DAD H instruction is same as |
| A. | shifting each bit one position to the left |
| B. | shifting each bit one position to the right |
| C. | shifting each bit one position to the left with a zero inserted in 1st position |
| D. | shifting each bit one position to the right with a zero inserted in 1st position |
| Answer» D. shifting each bit one position to the right with a zero inserted in 1st position | |
| 44. |
READY signal in 8085 is useful when the CPU communicates with |
| A. | a slow peripheral device |
| B. | a fast peripheral device |
| C. | a DMA controller chip |
| D. | a PPI chip |
| Answer» B. a fast peripheral device | |
| 45. |
Which of the following flag conditions are not available in 8085 processor? |
| A. | Zero flag |
| B. | Parity flag |
| C. | Overflow flag |
| D. | Auxiliary carry flag |
| Answer» D. Auxiliary carry flag | |
| 46. |
Every processor must necessarily have |
| A. | data bus |
| B. | data bus and address bus |
| C. | control bus |
| D. | data bus, a control bus and an address bus |
| Answer» E. | |
| 47. |
A high on RESET OUT line signifies that |
| A. | all the registers of the CPU are being reset |
| B. | all the registers and counters are being reset |
| C. | all the registers and counters are being reset and in addition this signal can be used to reset external support chips |
| D. | processing can begin when this signal goes high |
| Answer» D. processing can begin when this signal goes high | |
| 48. |
Normally a microprocessor cycles between |
| A. | Fetch and Halt states |
| B. | Fetch and Interrupt states |
| C. | Fetch and Execute states |
| D. | Halt and Execute states |
| Answer» D. Halt and Execute states | |
| 49. |
In 8085, interrupts excepts TRAP are disabled (check the incorrect statement) by |
| A. | a DI instruction |
| B. | a system reset |
| C. | acknowledgement of a previous interrupt |
| D. | none of these |
| Answer» E. | |
| 50. |
During a DMA transfer, the processor (check the incorrect statement) |
| A. | continues its normal operations |
| B. | suspends its normal operations |
| C. | needs to initiate read (write) command |
| D. | needs to check if the input/output device is ready for data transfer |
| Answer» B. suspends its normal operations | |