Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ________.

• A. <img src="/_files/images/digital-electronics/digital-fundamentals/cua7_0010a.gif">
• B. <img src="/_files/images/digital-electronics/digital-fundamentals/cua7_0010b.gif">
• C. <img src="/_files/images/digital-electronics/digital-fundamentals/cua7_0010c.gif">
• D. <img src="/_files/images/digital-electronics/digital-fundamentals/cua7_0010d.gif">