Match List I with List-II and select the correct answer using the code given below the lists: List I List IIA.Flash converter ADC1.Integrating typeB.Successive approximation ADC2.Fast conversionC.Counter ramp ADC3.Maximum conversion clock periods = Number of bitsD.Dual slope ADC4.Uses a DAC in its feedback path

A – 1, B – 3, C – 4, D - 2

A – 2, B – 3, C – 4, D - 1

A – 2, B – 4, C – 3, D - 1

A – 1, B – 4, C – 3, D - 2

Match List I with List-II and select the correct answer using the code

1.	Match List I with List-II and select the correct answer using the code given below the lists: List I List IIA.Flash converter ADC1.Integrating typeB.Successive approximation ADC2.Fast conversionC.Counter ramp ADC3.Maximum conversion clock periods = Number of bitsD.Dual slope ADC4.Uses a DAC in its feedback path
A.	A – 2, B – 3, C – 4, D - 1
B.	A – 1, B – 3, C – 4, D - 2
C.	A – 2, B – 4, C – 3, D - 1
D.	A – 1, B – 4, C – 3, D - 2
Answer» B. A – 1, B – 3, C – 4, D - 2

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