If a clock with time period 'T' is used with n stage shift register, t – McqOptions

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1.	If a clock with time period 'T' is used with n stage shift register, then output of final stage will be delayed by
A.	nT sec
B.	(n-1 )T sec
C.	n/T sec
D.	(2n-1) T sec
Answer» E.

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