For a pipelined CPU with a single ALU, consider the following situations1. The j + 1-st instruction uses the result of the j-th instruction as an operand2. The execution of a conditional jump instruction3. The j-th and j + 1-st instructions require the ALU at the same timeWhich of the above can cause a hazard ?

• A. 1 and 2 only
• B. 2 and 3 only
• C. 3 only
• D. All of above