Consider the following routing table at an IP router Q51 For each IP address in Group-I identify the correct choice of the next hop from Group-II using the entries from the routing table above. List-I List-II A. 128.96.171.92 1. Interface 0 B. 128.96.167.151 2. Interface 1 C. 128.96.163.121 3. R2 D. 128.96.165.121 4. R3 5. R4 Codes: A B C D (a) 1 3 5 4 (b) 1 4 2 5 (c) 2 3 4 5 (d) 2 3 5 4

Consider the following routing table at an IP router Q51 For each IP a

1.	Consider the following routing table at an IP router Q51 For each IP address in Group-I identify the correct choice of the next hop from Group-II using the entries from the routing table above. List-I List-II A. 128.96.171.92 1. Interface 0 B. 128.96.167.151 2. Interface 1 C. 128.96.163.121 3. R2 D. 128.96.165.121 4. R3 5. R4 Codes: A B C D (a) 1 3 5 4 (b) 1 4 2 5 (c) 2 3 4 5 (d) 2 3 5 4
A.	a
B.	b
C.	c
D.	d
Answer» B. b

Discussion

No Comment Found

Related MCQs

Let X and Y denote the sets containing 2 and 20 distinct objects respectively and F denote the set of all possible functions defined from X and Y. Let f be randomly chosen from F. The probability of f being one-to-one is _________
The number of states in the minimal deterministic finite automaton corresponding to the regular expression (0 + 1)*(10) is ____________
Host A sends a UDP datagram containing 8880 bytes of user data to host B over an Ethernet LAN. Ethernet frames may carry data up to 1500 bytes (i.e. MTU = 1500 bytes). Size of UDP header is 8 bytes and size of IP header is 20 bytes. There is no option field in IP header. How may total number of IP fragments will be transmitted and what will be the contents of offset field in the last fragment?
Which of the following languages is/are regular? L1: {wxwR ⎪ w, x ∈ {a, b}* and ⎪w⎪, ⎪x⎪ >0} wR is the reverse of string w L2: {anbm ⎪m ≠ n and m, n≥0 L3: {apbqcr ⎪ p, q, r ≥ 0}
In a connected graph, a bridge is an edge whose removal disconnects a graph. Which one of the following statements is True?
A Computer system implements 8 kilobyte pages and a 32-bit physical address space. Each page table entry contains a valid bit, a dirty bit three permission bits, and the translation. If the maximum size of the page table of a process is 24 megabytes, the length of the virtual address supported by the system is _______________ bits
Consider a simple checkpointing protocol and the following set of operations in the log. (start, T4); (write, T4, y, 2, 3); (start, T1); (commit, T4); (write, T1, z, 5, 7); (checkpoint); (start, T2); (write, T2, x, 1, 9); (commit, T2); (start, T3); (write, T3, z, 7, 2); If a crash happens now and the system tries to recover using both undo and redo operations, what are the contents of the undo list and the redo list
Suppose you are provided with the following function declaration in the C programming language. int partition (int a[], int n); The function treats the first element of a[] as a pivot, and rearranges the array so that all elements less than or equal to the pivot is in the left part of the array, and all elements greater than the pivot is in the right part. In addition, it moves the pivot so that the pivot is the last element of the left part. The return value is the number of elements in the left part. The following partially given function in the C programming language is used to find the kth smallest element in an array a[ ] of size n using the partition function. We assume k ≤ n int kth_smallest (int a[], int n, int k) { int left_end = partition (a, n); if (left_end+1==k) { return a [left_end]; } if (left_end+1 > k) { return kth_smallest (____________________); } else { return kth_smallest (____________________); } } The missing argument lists are respectively
Consider the sequence of machine instructions given below: MUL R5, R0, R1 DIV R6, R2, R3 ADD R7, R5, R6 SUB R8, R7, R4 In the above sequence, R0 to R8 are general purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perform Operation (PO) and (4) Write back the Result (WB). The IF, OF and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD or SUB instruction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is ___________
Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the main memory is implemented from memory location (0100)16 and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is (016E)16. The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word = 2 bytes). The CALL instruction is implemented as follows: • Store the current value of PC in the stack. • Store the value of PSW register in the stack. • Load the starting address of the subroutine in PC. The content of PC just before the fetch of a CALL instruction is (5FA0)16. After execution of the CALL instruction, the value of the stack pointer is

Discussion

No Comment Found

Related MCQs

Reply to Comment