A three-phase three pulse type controlled converter is constructed using 3 SCR devices. The circuit is supplying an R load with α < 30°. As such, each SCR device would conduct for

A three-phase three pulse type controlled converter is constructed usi

1.	A three-phase three pulse type controlled converter is constructed using 3 SCR devices. The circuit is supplying an R load with α < 30°. As such, each SCR device would conduct for
A.	60° each cycle
B.	120° each cycle
C.	180° each cycle
D.	360° each cycle
Answer» C. 180° each cycle

Discussion

No Comment Found

Related MCQs

An A-to-D converter in which one sub-circuit is a D-to-A converter is
For a 5-bit R-2R ladder D/A converter which has digital input of 10101, the analog output value is (Assume 0 = 0 V and 1 = + 10 V, Rf = 3R)
Analog-to-digital converter with the minimum number of bits that will convert analog input signals in the range of 0–5 V to an accuracy of 10 mV is
Match List I with List IIList IList IIA. Simplest type of ADC1. Flash – type ADCB. Fastest ADC2. dual – slope type ADCC. Slowest ADC3. counter – type ADCD. Most widely used ADC4. Successive – approximation type ADCChoose the correct answer from the options given below:
Consider the following Analog to Digital Converters:Counter type ADC: ADual slope ADC: BSAR type ADC: CFlash ADC: DThe correct order of conversion time (T) of the ADCs shown above is:
In a 4-bit R-2R ladder type digital-to-analog convertor with RF = R and VR= 5V, where RF and R are the feedback and input resistances respectively to realize the gain of the inverting amplifier using an op-amp, the resolution and full-scale output respectively are
An analog transducer with a 0 – 10 V input is able to distinguish a charge of 10 mV in its input signal. What is the number of bits of an A/D converter in binary code so that the digital output has almost the same resolution as the transducer?
Match the elements of List I and List IIList I(DVM)List III(Characteristic)a) Ramp-typei) Automatic zero correctionb) Dual-slope converterii) Linear ramp voltage rises from 0V to the level of input voltagec) Stair-case rampiii) Binary regressiond) Successive Approximationiv) Internally generated staircase ramp voltage Choose the correct option
Directions: It consists of two statements, one labelled as the ‘Statement (I)’ and the other as ‘Statement (II)’. Examine these two statements carefully and select the answers to these items using the codes given below:Statement (I):Flash analog-to-digital conversion is the fastest but an expensive method for designing ADCs.Statement (II):Flash analog-to-digital converters are employed on very high speed digital acquisition systems.
A 5 bit ladder has a digital input of 11010. Assuming that 0 corresponds to 0 V and 1 corresponds to +10 V, its output voltage will be:

A three-phase three pulse type controlled converter is constructed using 3 SCR devices. The circuit is supplying an R load with α < 30°. As such, each SCR device would conduct for

Discussion

No Comment Found

Related MCQs

Reply to Comment